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From Luis Vega <notificati...@github.com>
Subject Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware Simulation for VTA (#3009)
Date Fri, 12 Apr 2019 22:57:11 GMT
@jroesch 

There are two reasons why we have the two DPI modules in Verilog (Host and Memory):

1) To support either handwritten Verilog accelerators or generated Verilog from other languages
different than Chisel3

2) Chisel3 does not support DPI, which is the "CFFI" of Verilog. However, Chisel3 does support
Verilog inlining which is what we use for this so we don't duplicate code, see [here](https://github.com/dmlc/tvm/pull/3010/files#diff-dd8e52a607ff89a3d150245f3a1af322R52)

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