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From zfhn via TVM Discuss <>
Subject [TVM Discuss] [Development] [Tensor Expression] add hardware specific schedule
Date Thu, 21 Mar 2019 02:44:11 GMT

ring buffer optimization is common and critical on dsp(or other VLIW-like Asic). Except tvm
framwork can support this.

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Tianqi Chen, UW, Seattle, WA, 98105, United States
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