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From zfhn via TVM Discuss <nore...@discuss.tvm.ai>
Subject [TVM Discuss] [Development] [Tensor Expression] add hardware specific schedule
Date Thu, 21 Mar 2019 02:44:11 GMT


ring buffer optimization is common and critical on dsp(or other VLIW-like Asic). Except tvm
framwork can support this. 

https://discuss.tvm.ai/t/questions-about-memory-latency-hiding-on-dsp/1843





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[Visit Topic](https://discuss.tvm.ai/t/tensor-expression-add-hardware-specific-schedule/1893/16)
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