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From GitBox <...@apache.org>
Subject [GitHub] [incubator-tvm-vta] remotego commented on pull request #7: [pynq_driver] fix device early return
Date Thu, 30 Apr 2020 09:34:54 GMT

remotego commented on pull request #7:
URL: https://github.com/apache/incubator-tvm-vta/pull/7#issuecomment-621724098


   @huajsj Thank you for the reply. Let me explain more on this issue.
   
   The original name of 0x18 (24) register of Compute Module is XCOMPUTE_CONTROL_BUS_ADDR_DONE_O_DATA,
it is a output from the FPGA hardware. From the point of view of S/W, it is a read-only register.
Thus there is no way for software (i.e. driver) code to change the content of it. And this
register is fully controlled by FPGA H/W.
   
   ```
   impl/ip/drivers/compute_v1_0/src/xcompute_hw.h
   
   // 0x18 : Data signal of done_o
   //        bit 31~0 - done_o[31:0] (Read)
   ```
   
   If we trace the controlling of this register in h/w code, we could see the register will
be set to '0' at the beginning compute module, and sets to '1' only when a FINISH instruction
is encountered.
   
   ```
   void compute(
   ...
     // Set done value
     done = 0;
     // Perform action based on opcode
     if (insn.generic.opcode == VTA_OPCODE_FINISH) {
       // Set done flag if we reach a FINISH instruction
       done = 1;
     }
   ```
   
   When we start the VTA hardware by this code block,
   ```
       VTAWriteMappedReg(vta_fetch_handle_, 0x0, VTA_START);
       VTAWriteMappedReg(vta_load_handle_, 0x0, VTA_AUTORESTART);
       VTAWriteMappedReg(vta_compute_handle_, 0x0, VTA_AUTORESTART);
       VTAWriteMappedReg(vta_store_handle_, 0x0, VTA_AUTORESTART);
   ```
   The fetch module will dispatch the first compute instruction to compute module, and module
will then set the Done register to '0'.
   
   However, at the same time, the driver code will attempt to check the value of Done register
in a pooling loop. And if the Done register is equal to 1. the driver will break and return.
   ```
       if (flag == VTA_DONE) break;
   ```
   
   Thus we have a racing condition here:
   ```
   |START| ->|FPGA Compute module start|->|Done -> '0'|->|Other Computations...|->|Done
-> '1'|
             |                                                       |
             ->|Driver code attempts to check "done" register ??us |->
   ```


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