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From tqc...@apache.org
Subject [incubator-tvm] branch master updated (14ba49c -> 683ed4a)
Date Thu, 12 Mar 2020 03:59:11 GMT
This is an automated email from the ASF dual-hosted git repository.

tqchen pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-tvm.git.


    from 14ba49c  [refactor][relay pass] Separate analysis and transform passes (#5035)
     add 683ed4a  [VTA] VTA hardware/software codebase re-org (#5037)

No new revisions were added by this update.

Summary of changes:
 Makefile                                           |  2 +-
 apps/vta_rpc/start_rpc_server_to_tracker.sh        |  2 +-
 cmake/modules/VTA.cmake                            | 39 +++++-----
 docs/Doxyfile                                      |  2 +-
 docs/vta/dev/config.rst                            |  2 +-
 docs/vta/dev/hardware.rst                          | 12 +--
 docs/vta/install.md                                | 48 ++++++------
 tests/scripts/task_python_vta.sh                   | 41 -----------
 tests/scripts/task_python_vta_fsim.sh              |  2 +-
 tests/scripts/task_python_vta_tsim.sh              | 16 ++--
 vta/hardware/xilinx/README.md                      | 18 -----
 vta/python/vta/environment.py                      |  2 +-
 vta/python/vta/libinfo.py                          |  8 +-
 vta/python/vta/pkg_config.py                       | 10 +--
 vta/python/vta/testing/simulator.py                |  2 +-
 vta/{src => runtime}/device_api.cc                 |  2 +-
 vta/{src => runtime}/runtime.cc                    |  4 +-
 vta/{include/vta => runtime}/runtime.h             | 12 +--
 vta/tutorials/autotvm/tune_relay_vta.py            |  2 +-
 vta/tutorials/frontend/deploy_classification.py    |  2 +-
 vta/tutorials/frontend/deploy_detection.py         |  2 +-
 vta/tutorials/matrix_multiply.py                   |  2 +-
 vta/tutorials/optimize/convolution_opt.py          |  2 +-
 vta/tutorials/optimize/matrix_multiply_opt.py      |  2 +-
 vta/{ => vta-hw}/apps/gemm/CMakeLists.txt          | 12 +--
 vta/{ => vta-hw}/apps/gemm/Makefile                |  8 +-
 vta/{ => vta-hw}/apps/gemm/README.md               | 20 ++---
 .../apps/gemm/hardware/chisel/Makefile             |  2 +-
 .../apps/gemm}/hardware/chisel/build.sbt           |  0
 .../gemm}/hardware/chisel/project/build.properties |  2 +-
 .../apps/gemm/hardware/chisel/project/plugins.sbt  |  0
 .../chisel/src/main/scala/accel/Accel.scala        |  0
 .../chisel/src/main/scala/accel/Compute.scala      |  8 +-
 .../chisel/src/main/scala/accel/RegFile.scala      |  0
 .../chisel/src/test/scala/dut/TestAccel.scala      |  0
 .../apps/gemm}/python/__init__.py                  |  0
 .../apps/gemm}/python/tsim.py                      |  0
 vta/{ => vta-hw}/apps/gemm/src/driver.cc           |  0
 .../apps/gemm/tests/python/chisel_accel.py         |  0
 vta/{ => vta-hw}/apps/tsim_example/CMakeLists.txt  | 12 +--
 vta/{ => vta-hw}/apps/tsim_example/Makefile        |  4 +-
 vta/{ => vta-hw}/apps/tsim_example/README.md       | 16 ++--
 .../apps/tsim_example/hardware/chisel/Makefile     |  2 +-
 .../apps/tsim_example}/hardware/chisel/build.sbt   |  0
 .../hardware/chisel/project/build.properties       |  2 +-
 .../hardware/chisel/project/plugins.sbt            |  0
 .../chisel/src/main/scala/accel/Accel.scala        |  0
 .../chisel/src/main/scala/accel/Compute.scala      |  0
 .../chisel/src/main/scala/accel/RegFile.scala      |  0
 .../chisel/src/test/scala/dut/TestAccel.scala      |  0
 .../apps/tsim_example/hardware/verilog/Makefile    |  2 +-
 .../apps/tsim_example/hardware/verilog/src/Accel.v |  0
 .../tsim_example/hardware/verilog/src/Compute.v    |  0
 .../tsim_example/hardware/verilog/src/RegFile.v    |  0
 .../tsim_example/hardware/verilog/src/TestAccel.v  |  0
 .../apps/tsim_example}/python/__init__.py          |  0
 .../apps/tsim_example}/python/tsim.py              |  0
 vta/{ => vta-hw}/apps/tsim_example/src/driver.cc   |  0
 .../apps/tsim_example/tests/python/chisel_accel.py |  0
 .../tsim_example/tests/python/verilog_accel.py     |  0
 vta/{ => vta-hw}/config/README.md                  |  0
 vta/{ => vta-hw}/config/de10nano_sample.json       |  0
 vta/{ => vta-hw}/config/fsim_sample.json           |  0
 vta/{ => vta-hw}/config/pynq_sample.json           |  0
 vta/{ => vta-hw}/config/tsim_sample.json           |  0
 vta/{ => vta-hw}/config/ultra96_sample.json        |  0
 vta/{ => vta-hw}/config/vta_config.json            |  0
 vta/{ => vta-hw}/config/vta_config.py              |  6 +-
 vta/{ => vta-hw}/hardware/chisel/.gitignore        |  0
 vta/{ => vta-hw}/hardware/chisel/Makefile          | 85 +++++++++++-----------
 vta/{ => vta-hw}/hardware/chisel/README.md         |  6 +-
 vta/{ => vta-hw}/hardware/chisel/build.sbt         |  2 +-
 .../hardware/chisel/project/build.properties       |  2 +-
 .../hardware/chisel/project/plugins.sbt            |  0
 .../hardware/chisel/scalastyle-config.xml          |  0
 .../chisel/src/main/resources/verilog/VTAHostDPI.v |  0
 .../chisel/src/main/resources/verilog/VTAMemDPI.v  |  0
 .../chisel/src/main/resources/verilog/VTASimDPI.v  |  0
 .../chisel/src/main/scala/core/Compute.scala       |  0
 .../chisel/src/main/scala/core/Configs.scala       |  0
 .../hardware/chisel/src/main/scala/core/Core.scala |  0
 .../chisel/src/main/scala/core/Decode.scala        |  0
 .../chisel/src/main/scala/core/EventCounters.scala |  0
 .../chisel/src/main/scala/core/Fetch.scala         |  0
 .../hardware/chisel/src/main/scala/core/ISA.scala  |  0
 .../hardware/chisel/src/main/scala/core/Load.scala |  0
 .../chisel/src/main/scala/core/LoadUop.scala       |  0
 .../chisel/src/main/scala/core/Semaphore.scala     |  0
 .../chisel/src/main/scala/core/Store.scala         |  0
 .../chisel/src/main/scala/core/TensorAlu.scala     |  0
 .../chisel/src/main/scala/core/TensorGemm.scala    |  0
 .../chisel/src/main/scala/core/TensorLoad.scala    |  0
 .../chisel/src/main/scala/core/TensorStore.scala   |  0
 .../chisel/src/main/scala/core/TensorUtil.scala    |  0
 .../chisel/src/main/scala/core/package.scala       |  0
 .../chisel/src/main/scala/dpi/VTAHostDPI.scala     |  0
 .../chisel/src/main/scala/dpi/VTAMemDPI.scala      |  0
 .../chisel/src/main/scala/dpi/VTASimDPI.scala      |  0
 .../chisel/src/main/scala/interface/axi/AXI.scala  |  0
 .../chisel/src/main/scala/shell/Configs.scala      |  0
 .../chisel/src/main/scala/shell/IntelShell.scala   |  0
 .../chisel/src/main/scala/shell/SimShell.scala     |  0
 .../hardware/chisel/src/main/scala/shell/VCR.scala |  0
 .../hardware/chisel/src/main/scala/shell/VME.scala |  0
 .../chisel/src/main/scala/shell/VTAShell.scala     |  0
 .../chisel/src/main/scala/shell/XilinxShell.scala  |  0
 .../hardware/chisel/src/main/scala/test/Test.scala |  0
 .../chisel/src/main/scala/util/Config.scala        |  0
 .../scala/util/GenericParameterizedBundle.scala    |  0
 .../chisel/src/main/scala/vta/Configs.scala        |  0
 .../chisel/src/test/scala/unittest/AluTest.scala   | 22 +++---
 .../chisel/src/test/scala/unittest/Launcher.scala  |  8 +-
 .../chisel/src/test/scala/unittest/MvmTest.scala   | 16 ++--
 .../src/test/scala/unittest/utils/Helper.scala     |  0
 .../test/scala/unittest/utils/RandomArray.scala    |  0
 .../src/test/scala/unittest/utils/TestRunner.scala |  0
 vta/{ => vta-hw}/hardware/dpi/tsim_device.cc       |  0
 vta/{ => vta-hw}/hardware/intel/Makefile           |  0
 vta/{ => vta-hw}/hardware/intel/README.md          |  0
 .../hardware/intel/scripts/compile_design.tcl      | 10 +--
 .../hardware/intel/scripts/de10_nano_top.v         |  0
 .../hardware/intel/scripts/ip/vta/vta_hw.tcl       |  0
 .../hardware/intel/scripts/set_attrs.py            |  0
 .../hardware/intel/scripts/set_clocks.sdc          |  0
 .../hardware/intel/scripts/soc_system.tcl          |  0
 vta/{ => vta-hw}/hardware/xilinx/.gitignore        |  0
 vta/{ => vta-hw}/hardware/xilinx/Makefile          |  8 +-
 .../intel => vta-hw/hardware/xilinx}/README.md     |  0
 vta/{ => vta-hw}/hardware/xilinx/scripts/hls.tcl   |  4 +-
 vta/{ => vta-hw}/hardware/xilinx/scripts/hsi.tcl   |  4 +-
 .../hardware/xilinx/scripts/vivado.tcl             |  4 +-
 vta/{ => vta-hw}/hardware/xilinx/sim/vta_test.cc   |  4 +-
 vta/{ => vta-hw}/hardware/xilinx/src/vta.cc        |  4 +-
 vta/{ => vta-hw}/hardware/xilinx/src/vta.h         |  6 +-
 vta/{ => vta-hw}/include/vta/dpi/module.h          |  0
 vta/{ => vta-hw}/include/vta/dpi/tsim.h            |  0
 vta/{ => vta-hw}/include/vta/driver.h              |  0
 vta/{ => vta-hw}/include/vta/hw_spec.h             |  4 +-
 vta/{ => vta-hw}/include/vta/sim_tlpp.h            |  6 +-
 vta/{ => vta-hw}/src/de10nano/cma_api.cc           |  0
 vta/{ => vta-hw}/src/de10nano/cma_api.h            |  0
 vta/{ => vta-hw}/src/de10nano/de10nano_driver.cc   |  0
 vta/{ => vta-hw}/src/de10nano/de10nano_driver.h    |  0
 vta/{ => vta-hw}/src/de10nano/de10nano_mgr.h       |  0
 vta/{ => vta-hw}/src/dpi/module.cc                 |  0
 vta/{ => vta-hw}/src/pynq/pynq_driver.cc           |  0
 vta/{ => vta-hw}/src/pynq/pynq_driver.h            |  0
 vta/{ => vta-hw}/src/sim/sim_driver.cc             |  0
 vta/{ => vta-hw}/src/sim/sim_tlpp.cc               |  0
 vta/{ => vta-hw}/src/tsim/tsim_driver.cc           |  0
 vta/{ => vta-hw}/src/vmem/virtual_memory.cc        |  0
 vta/{ => vta-hw}/src/vmem/virtual_memory.h         |  0
 vta/{ => vta-hw}/tests/hardware/common/test_lib.cc |  4 +-
 vta/{ => vta-hw}/tests/hardware/common/test_lib.h  |  4 +-
 .../tests/hardware/metal_test/Makefile             |  0
 .../tests/hardware/metal_test/metal_test.cc        |  0
 156 files changed, 244 insertions(+), 291 deletions(-)
 delete mode 100755 tests/scripts/task_python_vta.sh
 delete mode 100644 vta/hardware/xilinx/README.md
 rename vta/{src => runtime}/device_api.cc (99%)
 rename vta/{src => runtime}/runtime.cc (99%)
 rename vta/{include/vta => runtime}/runtime.h (98%)
 rename vta/{ => vta-hw}/apps/gemm/CMakeLists.txt (81%)
 rename vta/{ => vta-hw}/apps/gemm/Makefile (87%)
 rename vta/{ => vta-hw}/apps/gemm/README.md (78%)
 rename vta/{ => vta-hw}/apps/gemm/hardware/chisel/Makefile (98%)
 rename vta/{apps/tsim_example => vta-hw/apps/gemm}/hardware/chisel/build.sbt (100%)
 rename vta/{apps/tsim_example => vta-hw/apps/gemm}/hardware/chisel/project/build.properties
(97%)
 rename vta/{ => vta-hw}/apps/gemm/hardware/chisel/project/plugins.sbt (100%)
 rename vta/{ => vta-hw}/apps/gemm/hardware/chisel/src/main/scala/accel/Accel.scala (100%)
 rename vta/{ => vta-hw}/apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala (98%)
 rename vta/{ => vta-hw}/apps/gemm/hardware/chisel/src/main/scala/accel/RegFile.scala (100%)
 rename vta/{apps/tsim_example => vta-hw/apps/gemm}/hardware/chisel/src/test/scala/dut/TestAccel.scala
(100%)
 rename vta/{apps/tsim_example => vta-hw/apps/gemm}/python/__init__.py (100%)
 rename vta/{apps/tsim_example => vta-hw/apps/gemm}/python/tsim.py (100%)
 rename vta/{ => vta-hw}/apps/gemm/src/driver.cc (100%)
 rename vta/{ => vta-hw}/apps/gemm/tests/python/chisel_accel.py (100%)
 rename vta/{ => vta-hw}/apps/tsim_example/CMakeLists.txt (81%)
 rename vta/{ => vta-hw}/apps/tsim_example/Makefile (96%)
 rename vta/{ => vta-hw}/apps/tsim_example/README.md (85%)
 rename vta/{ => vta-hw}/apps/tsim_example/hardware/chisel/Makefile (98%)
 rename vta/{apps/gemm => vta-hw/apps/tsim_example}/hardware/chisel/build.sbt (100%)
 rename vta/{apps/gemm => vta-hw/apps/tsim_example}/hardware/chisel/project/build.properties
(97%)
 rename vta/{ => vta-hw/apps/tsim_example}/hardware/chisel/project/plugins.sbt (100%)
 rename vta/{ => vta-hw}/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala
(100%)
 rename vta/{ => vta-hw}/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala
(100%)
 rename vta/{ => vta-hw}/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala
(100%)
 rename vta/{apps/gemm => vta-hw/apps/tsim_example}/hardware/chisel/src/test/scala/dut/TestAccel.scala
(100%)
 rename vta/{ => vta-hw}/apps/tsim_example/hardware/verilog/Makefile (98%)
 rename vta/{ => vta-hw}/apps/tsim_example/hardware/verilog/src/Accel.v (100%)
 rename vta/{ => vta-hw}/apps/tsim_example/hardware/verilog/src/Compute.v (100%)
 rename vta/{ => vta-hw}/apps/tsim_example/hardware/verilog/src/RegFile.v (100%)
 rename vta/{ => vta-hw}/apps/tsim_example/hardware/verilog/src/TestAccel.v (100%)
 rename vta/{apps/gemm => vta-hw/apps/tsim_example}/python/__init__.py (100%)
 rename vta/{apps/gemm => vta-hw/apps/tsim_example}/python/tsim.py (100%)
 rename vta/{ => vta-hw}/apps/tsim_example/src/driver.cc (100%)
 rename vta/{ => vta-hw}/apps/tsim_example/tests/python/chisel_accel.py (100%)
 rename vta/{ => vta-hw}/apps/tsim_example/tests/python/verilog_accel.py (100%)
 rename vta/{ => vta-hw}/config/README.md (100%)
 rename vta/{ => vta-hw}/config/de10nano_sample.json (100%)
 rename vta/{ => vta-hw}/config/fsim_sample.json (100%)
 rename vta/{ => vta-hw}/config/pynq_sample.json (100%)
 rename vta/{ => vta-hw}/config/tsim_sample.json (100%)
 rename vta/{ => vta-hw}/config/ultra96_sample.json (100%)
 rename vta/{ => vta-hw}/config/vta_config.json (100%)
 rename vta/{ => vta-hw}/config/vta_config.py (97%)
 rename vta/{ => vta-hw}/hardware/chisel/.gitignore (100%)
 rename vta/{ => vta-hw}/hardware/chisel/Makefile (75%)
 rename vta/{ => vta-hw}/hardware/chisel/README.md (98%)
 rename vta/{ => vta-hw}/hardware/chisel/build.sbt (98%)
 rename vta/{ => vta-hw}/hardware/chisel/project/build.properties (97%)
 rename vta/{apps/tsim_example => vta-hw}/hardware/chisel/project/plugins.sbt (100%)
 rename vta/{ => vta-hw}/hardware/chisel/scalastyle-config.xml (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/resources/verilog/VTAHostDPI.v (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/resources/verilog/VTAMemDPI.v (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/resources/verilog/VTASimDPI.v (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/Compute.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/Configs.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/Core.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/Decode.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/EventCounters.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/Fetch.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/ISA.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/Load.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/LoadUop.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/Semaphore.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/Store.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/TensorAlu.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/TensorGemm.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/TensorLoad.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/TensorStore.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/TensorUtil.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/core/package.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/interface/axi/AXI.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/shell/Configs.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/shell/IntelShell.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/shell/SimShell.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/shell/VCR.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/shell/VME.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/shell/VTAShell.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/shell/XilinxShell.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/test/Test.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/util/Config.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/util/GenericParameterizedBundle.scala
(100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/main/scala/vta/Configs.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/test/scala/unittest/AluTest.scala (96%)
 rename vta/{ => vta-hw}/hardware/chisel/src/test/scala/unittest/Launcher.scala (98%)
 rename vta/{ => vta-hw}/hardware/chisel/src/test/scala/unittest/MvmTest.scala (97%)
 rename vta/{ => vta-hw}/hardware/chisel/src/test/scala/unittest/utils/Helper.scala (100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/test/scala/unittest/utils/RandomArray.scala
(100%)
 rename vta/{ => vta-hw}/hardware/chisel/src/test/scala/unittest/utils/TestRunner.scala
(100%)
 rename vta/{ => vta-hw}/hardware/dpi/tsim_device.cc (100%)
 rename vta/{ => vta-hw}/hardware/intel/Makefile (100%)
 copy vta/{ => vta-hw}/hardware/intel/README.md (100%)
 rename vta/{ => vta-hw}/hardware/intel/scripts/compile_design.tcl (99%)
 rename vta/{ => vta-hw}/hardware/intel/scripts/de10_nano_top.v (100%)
 rename vta/{ => vta-hw}/hardware/intel/scripts/ip/vta/vta_hw.tcl (100%)
 rename vta/{ => vta-hw}/hardware/intel/scripts/set_attrs.py (100%)
 rename vta/{ => vta-hw}/hardware/intel/scripts/set_clocks.sdc (100%)
 rename vta/{ => vta-hw}/hardware/intel/scripts/soc_system.tcl (100%)
 rename vta/{ => vta-hw}/hardware/xilinx/.gitignore (100%)
 rename vta/{ => vta-hw}/hardware/xilinx/Makefile (92%)
 rename vta/{hardware/intel => vta-hw/hardware/xilinx}/README.md (100%)
 rename vta/{ => vta-hw}/hardware/xilinx/scripts/hls.tcl (99%)
 rename vta/{ => vta-hw}/hardware/xilinx/scripts/hsi.tcl (99%)
 rename vta/{ => vta-hw}/hardware/xilinx/scripts/vivado.tcl (99%)
 rename vta/{ => vta-hw}/hardware/xilinx/sim/vta_test.cc (99%)
 rename vta/{ => vta-hw}/hardware/xilinx/src/vta.cc (99%)
 rename vta/{ => vta-hw}/hardware/xilinx/src/vta.h (99%)
 rename vta/{ => vta-hw}/include/vta/dpi/module.h (100%)
 rename vta/{ => vta-hw}/include/vta/dpi/tsim.h (100%)
 rename vta/{ => vta-hw}/include/vta/driver.h (100%)
 rename vta/{ => vta-hw}/include/vta/hw_spec.h (99%)
 rename vta/{ => vta-hw}/include/vta/sim_tlpp.h (99%)
 rename vta/{ => vta-hw}/src/de10nano/cma_api.cc (100%)
 rename vta/{ => vta-hw}/src/de10nano/cma_api.h (100%)
 rename vta/{ => vta-hw}/src/de10nano/de10nano_driver.cc (100%)
 rename vta/{ => vta-hw}/src/de10nano/de10nano_driver.h (100%)
 rename vta/{ => vta-hw}/src/de10nano/de10nano_mgr.h (100%)
 rename vta/{ => vta-hw}/src/dpi/module.cc (100%)
 rename vta/{ => vta-hw}/src/pynq/pynq_driver.cc (100%)
 rename vta/{ => vta-hw}/src/pynq/pynq_driver.h (100%)
 rename vta/{ => vta-hw}/src/sim/sim_driver.cc (100%)
 rename vta/{ => vta-hw}/src/sim/sim_tlpp.cc (100%)
 rename vta/{ => vta-hw}/src/tsim/tsim_driver.cc (100%)
 rename vta/{ => vta-hw}/src/vmem/virtual_memory.cc (100%)
 rename vta/{ => vta-hw}/src/vmem/virtual_memory.h (100%)
 rename vta/{ => vta-hw}/tests/hardware/common/test_lib.cc (99%)
 rename vta/{ => vta-hw}/tests/hardware/common/test_lib.h (99%)
 rename vta/{ => vta-hw}/tests/hardware/metal_test/Makefile (100%)
 rename vta/{ => vta-hw}/tests/hardware/metal_test/metal_test.cc (100%)


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