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From GitBox <...@apache.org>
Subject [GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Date Sat, 07 Mar 2020 17:09:45 GMT
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and
de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389279439
 
 

 ##########
 File path: vta/hardware/intel/scripts/soc_system.tcl
 ##########
 @@ -88,34 +237,486 @@ set_instance_parameter_value hps_0 {MEM_VENDOR} {Other}
 set_instance_parameter_value hps_0 {MEM_VERBOSE} {1}
 set_instance_parameter_value hps_0 {MEM_VOLTAGE} {1.5V DDR3}
 set_instance_parameter_value hps_0 {MEM_WTCL} {7}
-set_instance_parameter_value hps_0 {F2SCLK_COLDRST_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_DBGRST_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_PERIPHCLK_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_SDRAMCLK_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_WARMRST_Enable} {0}
-set_instance_parameter_value hps_0 {LWH2F_Enable} {true}
-set_instance_parameter_value hps_0 {S2F_Width} {0}
-set_instance_parameter_value hps_0 {F2SDRAM_Type} {}
-set_instance_parameter_value hps_0 {F2SDRAM_Width} {}
 set_instance_parameter_value hps_0 {MPU_EVENTS_Enable} {0}
+set_instance_parameter_value hps_0 {MRS_MIRROR_PING_PONG_ATSO} {0}
+set_instance_parameter_value hps_0 {MULTICAST_EN} {0}
+set_instance_parameter_value hps_0 {NAND_Mode} {N/A}
+set_instance_parameter_value hps_0 {NAND_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {NEXTGEN} {1}
+set_instance_parameter_value hps_0 {NIOS_ROM_DATA_WIDTH} {32}
+set_instance_parameter_value hps_0 {NUM_DLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {NUM_EXTRA_REPORT_PATH} {10}
+set_instance_parameter_value hps_0 {NUM_OCT_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {NUM_OF_PORTS} {1}
+set_instance_parameter_value hps_0 {NUM_PLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {OCT_SHARING_MODE} {None}
+set_instance_parameter_value hps_0 {P2C_READ_CLOCK_ADD_PHASE} {0.0}
+set_instance_parameter_value hps_0 {PACKAGE_DESKEW} {0}
+set_instance_parameter_value hps_0 {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM} {}
+set_instance_parameter_value hps_0 {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {PHY_CSR_CONNECTION} {INTERNAL_JTAG}
+set_instance_parameter_value hps_0 {PHY_CSR_ENABLED} {0}
+set_instance_parameter_value hps_0 {PHY_ONLY} {0}
+set_instance_parameter_value hps_0 {PINGPONGPHY_EN} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_CLK_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_LOCATION} {Top_Bottom}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_SHARING_MODE} {None}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {POWER_OF_TWO_BUS} {0}
+set_instance_parameter_value hps_0 {PRIORITY_PORT} {1 1 1 1 1 1}
+set_instance_parameter_value hps_0 {QSPI_Mode} {N/A}
+set_instance_parameter_value hps_0 {QSPI_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {RATE} {Full}
+set_instance_parameter_value hps_0 {RDIMM_CONFIG} {0000000000000000}
+set_instance_parameter_value hps_0 {READ_DQ_DQS_CLOCK_SOURCE} {INVERTED_DQS_BUS}
+set_instance_parameter_value hps_0 {READ_FIFO_SIZE} {8}
+set_instance_parameter_value hps_0 {REFRESH_BURST_VALIDATION} {0}
+set_instance_parameter_value hps_0 {REFRESH_INTERVAL} {15000}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ} {125.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_MAX_PARAM} {0.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_MIN_PARAM} {0.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {S2FCLK_COLDRST_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_PENDINGRST_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER0CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER1CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER1CLK_FREQ} {100.0}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK} {5}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK_FREQ} {100.0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CAN_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CLOCKPERIPHERAL_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CTI_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_DMA_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_EMAC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_FPGAMANAGER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_GPIO_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_I2CEMAC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_I2CPERIPHERAL_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_L4TIMER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_NAND_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_OSCTIMER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_QSPI_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SDMMC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SPIMASTER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SPISLAVE_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_UART_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_USB_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_WATCHDOG_Enable} {0}
+set_instance_parameter_value hps_0 {S2F_Width} {0}
+set_instance_parameter_value hps_0 {SDIO_Mode} {N/A}
+set_instance_parameter_value hps_0 {SDIO_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SEQUENCER_TYPE} {NIOS}
+set_instance_parameter_value hps_0 {SEQ_MODE} {0}
+set_instance_parameter_value hps_0 {SKIP_MEM_INIT} {1}
+set_instance_parameter_value hps_0 {SOPC_COMPAT_RESET} {0}
+set_instance_parameter_value hps_0 {SPEED_GRADE} {7}
+set_instance_parameter_value hps_0 {SPIM0_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIM0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIM1_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIM1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIS0_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIS0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIS1_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIS1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {STARVE_LIMIT} {10}
+set_instance_parameter_value hps_0 {STM_Enable} {0}
+set_instance_parameter_value hps_0 {TEST_Enable} {0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_EYE_REDUCTION_H} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_EYE_REDUCTION_SU} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_SKEW} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_SLEW_RATE} {1.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_CK_CKN_SLEW_RATE} {2.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DERATE_METHOD} {AUTO}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQS_DQSN_SLEW_RATE} {2.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_SLEW_RATE} {1.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_ISI_METHOD} {AUTO}
+set_instance_parameter_value hps_0 {TIMING_BOARD_MAX_CK_DELAY} {0.6}
+set_instance_parameter_value hps_0 {TIMING_BOARD_MAX_DQS_DELAY} {0.6}
+set_instance_parameter_value hps_0 {TIMING_BOARD_READ_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_BETWEEN_DIMMS} {0.05}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.01}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {-0.01}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_WITHIN_DQS} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TDH} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TDS} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TIH} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TIS} {0.0}
+set_instance_parameter_value hps_0 {TIMING_TDH} {125}
+set_instance_parameter_value hps_0 {TIMING_TDQSCK} {400}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDL} {1200}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDM} {900}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDS} {450}
+set_instance_parameter_value hps_0 {TIMING_TDQSH} {0.35}
+set_instance_parameter_value hps_0 {TIMING_TDQSQ} {120}
+set_instance_parameter_value hps_0 {TIMING_TDQSS} {0.25}
+set_instance_parameter_value hps_0 {TIMING_TDS} {50}
+set_instance_parameter_value hps_0 {TIMING_TDSH} {0.2}
+set_instance_parameter_value hps_0 {TIMING_TDSS} {0.2}
+set_instance_parameter_value hps_0 {TIMING_TIH} {250}
+set_instance_parameter_value hps_0 {TIMING_TIS} {175}
+set_instance_parameter_value hps_0 {TIMING_TQH} {0.38}
+set_instance_parameter_value hps_0 {TIMING_TQHS} {300}
+set_instance_parameter_value hps_0 {TIMING_TQSH} {0.38}
+set_instance_parameter_value hps_0 {TPIUFPGA_Enable} {0}
+set_instance_parameter_value hps_0 {TPIUFPGA_alt} {0}
+set_instance_parameter_value hps_0 {TRACE_Mode} {N/A}
+set_instance_parameter_value hps_0 {TRACE_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {TRACKING_ERROR_TEST} {0}
+set_instance_parameter_value hps_0 {TRACKING_WATCH_TEST} {0}
+set_instance_parameter_value hps_0 {TREFI} {35100}
+set_instance_parameter_value hps_0 {TRFC} {350}
+set_instance_parameter_value hps_0 {UART0_Mode} {N/A}
+set_instance_parameter_value hps_0 {UART0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {UART1_Mode} {N/A}
+set_instance_parameter_value hps_0 {UART1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USB0_Mode} {N/A}
+set_instance_parameter_value hps_0 {USB0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USB1_Mode} {N/A}
+set_instance_parameter_value hps_0 {USB1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USER_DEBUG_LEVEL} {1}
+set_instance_parameter_value hps_0 {USE_AXI_ADAPTOR} {0}
+set_instance_parameter_value hps_0 {USE_FAKE_PHY} {0}
+set_instance_parameter_value hps_0 {USE_MEM_CLK_FREQ} {0}
+set_instance_parameter_value hps_0 {USE_MM_ADAPTOR} {1}
+set_instance_parameter_value hps_0 {USE_SEQUENCER_BFM} {0}
+set_instance_parameter_value hps_0 {WEIGHT_PORT} {0 0 0 0 0 0}
+set_instance_parameter_value hps_0 {WRBUFFER_ADDR_WIDTH} {6}
+set_instance_parameter_value hps_0 {can0_clk_div} {1}
+set_instance_parameter_value hps_0 {can1_clk_div} {1}
+set_instance_parameter_value hps_0 {configure_advanced_parameters} {0}
+set_instance_parameter_value hps_0 {customize_device_pll_info} {0}
+set_instance_parameter_value hps_0 {dbctrl_stayosc1} {1}
+set_instance_parameter_value hps_0 {dbg_at_clk_div} {0}
+set_instance_parameter_value hps_0 {dbg_clk_div} {1}
+set_instance_parameter_value hps_0 {dbg_trace_clk_div} {0}
+set_instance_parameter_value hps_0 {desired_can0_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_can1_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_cfg_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_emac0_clk_mhz} {250.0}
+set_instance_parameter_value hps_0 {desired_emac1_clk_mhz} {250.0}
+set_instance_parameter_value hps_0 {desired_gpio_db_clk_hz} {32000}
+set_instance_parameter_value hps_0 {desired_l4_mp_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_l4_sp_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_mpu_clk_mhz} {800.0}
+set_instance_parameter_value hps_0 {desired_nand_clk_mhz} {12.5}
+set_instance_parameter_value hps_0 {desired_qspi_clk_mhz} {400.0}
+set_instance_parameter_value hps_0 {desired_sdmmc_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {desired_spi_m_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {desired_usb_mp_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {device_pll_info_manual} {{320000000 1600000000} {320000000
1000000000} {800000000 400000000 400000000}}
+set_instance_parameter_value hps_0 {eosc1_clk_mhz} {25.0}
+set_instance_parameter_value hps_0 {eosc2_clk_mhz} {25.0}
+set_instance_parameter_value hps_0 {gpio_db_clk_div} {6249}
+set_instance_parameter_value hps_0 {l3_mp_clk_div} {1}
+set_instance_parameter_value hps_0 {l3_sp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_mp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_mp_clk_source} {1}
+set_instance_parameter_value hps_0 {l4_sp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_sp_clk_source} {1}
+set_instance_parameter_value hps_0 {main_pll_c3} {3}
+set_instance_parameter_value hps_0 {main_pll_c4} {3}
+set_instance_parameter_value hps_0 {main_pll_c5} {15}
+set_instance_parameter_value hps_0 {main_pll_m} {63}
+set_instance_parameter_value hps_0 {main_pll_n} {0}
+set_instance_parameter_value hps_0 {nand_clk_source} {2}
+set_instance_parameter_value hps_0 {periph_pll_c0} {3}
+set_instance_parameter_value hps_0 {periph_pll_c1} {3}
+set_instance_parameter_value hps_0 {periph_pll_c2} {1}
+set_instance_parameter_value hps_0 {periph_pll_c3} {19}
+set_instance_parameter_value hps_0 {periph_pll_c4} {4}
+set_instance_parameter_value hps_0 {periph_pll_c5} {9}
+set_instance_parameter_value hps_0 {periph_pll_m} {79}
+set_instance_parameter_value hps_0 {periph_pll_n} {1}
+set_instance_parameter_value hps_0 {periph_pll_source} {0}
+set_instance_parameter_value hps_0 {qspi_clk_source} {1}
+set_instance_parameter_value hps_0 {sdmmc_clk_source} {2}
+set_instance_parameter_value hps_0 {show_advanced_parameters} {0}
+set_instance_parameter_value hps_0 {show_debug_info_as_warning_msg} {0}
+set_instance_parameter_value hps_0 {show_warning_as_error_msg} {0}
+set_instance_parameter_value hps_0 {spi_m_clk_div} {0}
+set_instance_parameter_value hps_0 {usb_mp_clk_div} {0}
+set_instance_parameter_value hps_0 {use_default_mpu_clk} {1}
 
-add_instance vta_0 vta 1.0
-
-# connections and connection parameters
-add_connection clk_0.clk hps_0.f2h_axi_clock clock
-add_connection clk_0.clk hps_0.h2f_lw_axi_clock clock
-add_connection clk_0.clk vta_0.clock clock
-add_connection clk_0.clk_reset vta_0.reset reset
-
-add_connection hps_0.h2f_lw_axi_master vta_0.s_axi_control avalon
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control arbitrationPriority
{1}
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control baseAddress {0x00020000}
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control defaultConnection
{0}
+add_instance pll_0 altera_pll 18.1
+set_instance_parameter_value pll_0 {debug_print_output} {0}
+set_instance_parameter_value pll_0 {debug_use_rbc_taf_method} {0}
+set_instance_parameter_value pll_0 {gui_active_clk} {0}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency0} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency1} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency10} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency11} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency12} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency13} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency14} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency15} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency16} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency17} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency2} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency3} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency4} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency5} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency6} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency7} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency8} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency9} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift0} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift1} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift10} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift11} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift12} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift13} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift14} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift15} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift16} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift17} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift2} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift3} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift4} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift5} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift6} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift7} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift8} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift9} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter0} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter1} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter10} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter11} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter12} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter13} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter14} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter15} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter16} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter17} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter2} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter3} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter4} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter5} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter6} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter7} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter8} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter9} {0}
+set_instance_parameter_value pll_0 {gui_cascade_outclk_index} {0}
+set_instance_parameter_value pll_0 {gui_channel_spacing} {0.0}
+set_instance_parameter_value pll_0 {gui_clk_bad} {0}
+set_instance_parameter_value pll_0 {gui_device_speed_grade} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c0} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c1} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c10} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c11} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c12} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c13} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c14} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c15} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c16} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c17} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c2} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c3} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c4} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c5} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c6} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c7} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c8} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c9} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_n} {1}
+set_instance_parameter_value pll_0 {gui_dps_cntr} {C0}
+set_instance_parameter_value pll_0 {gui_dps_dir} {Positive}
+set_instance_parameter_value pll_0 {gui_dps_num} {1}
+set_instance_parameter_value pll_0 {gui_dsm_out_sel} {1st_order}
+set_instance_parameter_value pll_0 {gui_duty_cycle0} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle1} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle10} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle11} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle12} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle13} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle14} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle15} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle16} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle17} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle2} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle3} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle4} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle5} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle6} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle7} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle8} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle9} {50}
+set_instance_parameter_value pll_0 {gui_en_adv_params} {0}
+set_instance_parameter_value pll_0 {gui_en_dps_ports} {0}
+set_instance_parameter_value pll_0 {gui_en_phout_ports} {0}
+set_instance_parameter_value pll_0 {gui_en_reconf} {0}
+set_instance_parameter_value pll_0 {gui_enable_cascade_in} {0}
+set_instance_parameter_value pll_0 {gui_enable_cascade_out} {0}
+set_instance_parameter_value pll_0 {gui_enable_mif_dps} {0}
+set_instance_parameter_value pll_0 {gui_feedback_clock} {Global Clock}
+set_instance_parameter_value pll_0 {gui_frac_multiply_factor} {1.0}
+set_instance_parameter_value pll_0 {gui_fractional_cout} {32}
+set_instance_parameter_value pll_0 {gui_mif_generate} {0}
+set_instance_parameter_value pll_0 {gui_multiply_factor} {1}
+set_instance_parameter_value pll_0 {gui_number_of_clocks} {1}
+set_instance_parameter_value pll_0 {gui_operation_mode} {normal}
+set_instance_parameter_value pll_0 {gui_output_clock_frequency0} $FREQ_MHZ
+set_instance_parameter_value pll_0 {gui_output_clock_frequency1} {100.0}
 
 Review comment:
   No, only output 0 of the PLL is used to feed clock to VTA.
   All other output are unused.

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