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From "Caldarale, Charles R" <>
Subject RE: [OT] IIS7/isapi/tomcat performance
Date Tue, 01 Mar 2011 23:42:51 GMT
> From: Christopher Schultz [] 
> Subject: Re: [OT] IIS7/isapi/tomcat performance

> The question I have is how does the bus controller know 
> that there are multiple 32-bit values coming down the line,
> and that it can send them simultaneously down the bus?

A traditional "bus controller" hasn't been used in quite some time, and buses themselves are
rapidly being replaced by point-to-point connections (finally), at least in terms of CPUs
accessing memory.  The interface between the L1 operand cache and the multiple ALUs is under
control of a scheduler that's aware of the possible 72 simultaneous loads and stores going
on, so it can combine accesses as it sees fit.  Accesses between lower-level caches and actual
RAM have always been wider than the data path within a core.

> There's more data to be sent over the bus than just pointers 
> to other pieces of data.

Of course - except there is no "the bus".

> You have to move the instruction itself

Not these days.  The instruction will be loaded from memory once, broken (and combined) into
micro-ops, and those are stored in the instruction cache.  If you're getting i-cache much
beyond single digit percentages, your performance will be horrible.

> so there's lots of opportunities for other data
> to get in the way of this "DRR-style" data transfer
> across the bus.

Your continued use of the phrase "the bus" is rather quaint...

> that would only affect the processing of, say, a 64-bit pointer 
> within the core...

No, it affects all data, not just pointers.

> I'd love to see some real documentation and/or testing on this 
> type of stuff.

Start with this one:

> my intuition tells me that the CPU and bus aren't magic :)

Compared to just a few years ago, they are.

 - Chuck

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