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From "Caldarale, Charles R" <Chuck.Caldar...@unisys.com>
Subject RE: [OT] IIS7/isapi/tomcat performance
Date Tue, 01 Mar 2011 23:09:10 GMT
> From: Christopher Schultz [mailto:chris@christopherschultz.net] 
> Subject: Re: [OT] IIS7/isapi/tomcat performance

> I don't understand why communicating a 64-bit value over a 
> 64-bit bus would take longer than communicating a 32-bit 
> value over a 64-bit bus:

Because you get *two* 32-bit values for one transfer, not just one. 
 
BTW, it's somewhat pointless to use the unqualified term "bus" when referring to modern CPU
architecture.  Now that Intel has finally figured out how to make multi-processor systems
run at a reasonable speed by using techniques we implemented back in the 1960s, along with
the advent of multiple memory cache levels, there's no longer a single bus to be concerned
with.  Most of them are wider than 64 bits in order to move as much data as possible; even
ten years ago, Intel was moving 64 _bytes_ at a time on most of the data paths.

> I also get that some processors (like Itanium) have an x84
> processor core on the die

(Presumably, you meant x86.)  Sorry, Itanium was notoriously bad at running 32-bit apps.

> getting the data from point A to point B shouldn't matter

Sure it does, if you can batch multiple operand accesses together (which current Intel cores
do).

> I suppose of the CPU knew it was in a 32-bit mode, it could 
> adjust the number of clock ticks it had to wait around for 
> 32-bit data to go through an adder, but that seems overly 
> complicated for a straightforward CPU task.

Simple adders have only used one cycle for decades, regardless of the width.

 - Chuck


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