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From Christopher Schultz <>
Subject Re: [OT] IIS7/isapi/tomcat performance
Date Thu, 03 Mar 2011 02:26:30 GMT
Hash: SHA1


On 3/1/2011 6:09 PM, Caldarale, Charles R wrote:
>> From: Christopher Schultz [] 
>> Subject: Re: [OT] IIS7/isapi/tomcat performance
>> I don't understand why communicating a 64-bit value over a 
>> 64-bit bus would take longer than communicating a 32-bit 
>> value over a 64-bit bus:
> Because you get *two* 32-bit values for one transfer, not just one. 

If, as you say, Intel can move 64 /bytes/ across a data path (if you
prefer that phrase over "the bus") then the word size really does make a
difference, here. They should be getting 16 32-bit words across such a
data path or 8 64-bit words.

If the pointers are doubling in size, this makes 64-bit mode go slower
because you get half the throughput when using word-sized values. Since
pointers in general are word-sized, they always suffer while other
(usually smaller) data does not.

The key is that the data path(s) are actually much wider than the word
size, which I didn't realize.

>> I also get that some processors (like Itanium) have an x84
>> processor core on the die
> (Presumably, you meant x86.)  Sorry, Itanium was notoriously bad at running 32-bit apps.

I did mean x86. Lots of typing yesterday. The new Itaniums are supposed
to be actually worth it, though.

>> getting the data from point A to point B shouldn't matter
> Sure it does, if you can batch multiple operand accesses together (which current Intel
cores do).
>> I suppose of the CPU knew it was in a 32-bit mode, it could 
>> adjust the number of clock ticks it had to wait around for 
>> 32-bit data to go through an adder, but that seems overly 
>> complicated for a straightforward CPU task.
> Simple adders have only used one cycle for decades, regardless of the width.

If the clock tick is long enough :)

- -chris
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