Return-Path: Delivered-To: apmail-incubator-stdcxx-dev-archive@www.apache.org Received: (qmail 81436 invoked from network); 25 Aug 2005 16:32:51 -0000 Received: from hermes.apache.org (HELO mail.apache.org) (209.237.227.199) by minotaur.apache.org with SMTP; 25 Aug 2005 16:32:51 -0000 Received: (qmail 86909 invoked by uid 500); 25 Aug 2005 16:32:51 -0000 Delivered-To: apmail-incubator-stdcxx-dev-archive@incubator.apache.org Received: (qmail 86889 invoked by uid 500); 25 Aug 2005 16:32:51 -0000 Mailing-List: contact stdcxx-dev-help@incubator.apache.org; run by ezmlm Precedence: bulk List-Help: List-Unsubscribe: List-Post: List-Id: Reply-To: stdcxx-dev@incubator.apache.org Delivered-To: mailing list stdcxx-dev@incubator.apache.org Received: (qmail 86874 invoked by uid 99); 25 Aug 2005 16:32:50 -0000 Received: from asf.osuosl.org (HELO asf.osuosl.org) (140.211.166.49) by apache.org (qpsmtpd/0.29) with ESMTP; Thu, 25 Aug 2005 09:32:50 -0700 X-ASF-Spam-Status: No, hits=0.0 required=10.0 tests= X-Spam-Check-By: apache.org Received-SPF: pass (asf.osuosl.org: local policy) Received: from [12.17.213.84] (HELO bco-exchange.bco.roguewave.com) (12.17.213.84) by apache.org (qpsmtpd/0.29) with ESMTP; Thu, 25 Aug 2005 09:33:08 -0700 Received: from [10.70.3.113] (10.70.3.113 [10.70.3.113]) by bco-exchange.bco.roguewave.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2657.72) id NNYTQ82K; Thu, 25 Aug 2005 10:32:22 -0600 Message-ID: <430DF31C.90701@roguewave.com> Date: Thu, 25 Aug 2005 10:34:36 -0600 From: Martin Sebor User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.7.10) Gecko/20050716 X-Accept-Language: en-us, en MIME-Version: 1.0 To: stdcxx-dev@incubator.apache.org Subject: Re: FW: [PATCH] STDCXX-11: IA64 32-bit atomic operations broken References: <4FA4B7B3231C5D459E7BAD020213A94202948E52@bco-exchange.bco.roguewave.com> In-Reply-To: <4FA4B7B3231C5D459E7BAD020213A94202948E52@bco-exchange.bco.roguewave.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Virus-Checked: Checked by ClamAV on apache.org X-Spam-Rating: minotaur.apache.org 1.6.2 0/1000/N Nicole Willson wrote: > Here is the patch for atomic-ia64-32.s: Thanks, but didn't we already get this patch here: http://mail-archives.apache.org/mod_mbox/incubator-stdcxx-dev/200508.mbox/%3c4FA4B7B3231C5D459E7BAD020213A94202948E29@bco-exchange.bco.roguewave.com%3e Martin > > Start of src/atomic-ia64-32.s > ------------------------------------------------------------------- > //////////////////////////////////////////////////////////////////////////// > // > // atomic-ia64-32.s > // > // $Id: //stdlib/4.1.1-rel/source/stdlib/atomic-ia64-32.s#1 $ > // > //////////////////////////////////////////////////////////////////////////// > > .text > //.pred.safe_across_calls p1-p5,p16-p63 > .psr abi32 > .psr msb > > //////////////////////////////////////////////////////////////////////////// > // extern "C" char __rw_atomic_xchg8 (char *x, char y); > // > // Atomically assigns the 8-bit value y to *x and returns > // the original (before assignment) 8-bit value of *x. > //////////////////////////////////////////////////////////////////////////// > > .global __rw_atomic_xchg8# > .proc __rw_atomic_xchg8# > > __rw_atomic_xchg8: > > .prologue > .body > // .mfb > addp4 r9 = 0, r32 // Needed to be able to dereference a 32 bit > pointer > ;; > xchg1 r8 = [r9], r33 > nop 0 > br.ret.sptk.many b0 > > .endp __rw_atomic_xchg8# > > //////////////////////////////////////////////////////////////////////////// > // extern "C" char __rw_atomic_add8 (char *x, int y); > // > // Atomically increments the 8-bit value *x by y and returns > // the new (after increment) 8-bit value of *x. > //////////////////////////////////////////////////////////////////////////// > > .global __rw_atomic_add8# > .proc __rw_atomic_add8# > > __rw_atomic_add8: > > .prologue > .body > // .mmb > mf > addp4 r9 = 0, r32 // Needed to be able to dereference a 32 bit > pointer > ;; > ld1.acq r15 = [r9] > nop 0 > ;; > .add8_busywait: > // .mmi > mov ar.ccv = r15 > add r8 = r15, r33 > mov r2 = r15 > ;; > // .mmb > nop 0 > cmpxchg1.acq r15 = [r9], r8, ar.ccv > nop 0 > ;; > // .mbb > cmp.ne p8, p9 = r2, r15 > (p9) br.ret.dpnt.many rp > br .add8_busywait > > .endp __rw_atomic_add8# > > //////////////////////////////////////////////////////////////////////////// > // extern "C" short __rw_atomic_xchg16 (short *x, short y); > // > // Atomically assigns the 16-bit value y to *x and returns > // the original (before assignment) 16-bit value of *x. > //////////////////////////////////////////////////////////////////////////// > > .global __rw_atomic_xchg16# > .proc __rw_atomic_xchg16# > > __rw_atomic_xchg16: > > .prologue > .body > // .mfb > addp4 r9 = 0, r32 // Needed to be able to dereference a 32 bit > pointer > ;; > xchg2 r8 = [r9], r33 > nop 0 > br.ret.sptk.many b0 > > .endp __rw_atomic_xchg16# > > //////////////////////////////////////////////////////////////////////////// > // extern "C" short __rw_atomic_add16 (short *x, short y); > // > // Atomically increments the 16-bit value *x by y and returns > // the new (after increment) 16-bit value of *x. > //////////////////////////////////////////////////////////////////////////// > > .global __rw_atomic_add16# > .proc __rw_atomic_add16# > > __rw_atomic_add16: > > .prologue > .body > // .mmb > mf > addp4 r9 = 0, r32 // Needed to be able to dereference a 32 bit > pointer > ;; > ld2.acq r15 = [r9] > nop 0 > ;; > .add16_busywait: > // .mmi > mov ar.ccv = r15 > add r8 = r15, r33 > mov r2 = r15 > ;; > // .mmb > nop 0 > cmpxchg2.acq r15 = [r9], r8, ar.ccv > nop 0 > ;; > // .mbb > cmp.ne p8, p9 = r2, r15 > (p9) br.ret.dpnt.many rp > br .add16_busywait > > .endp __rw_atomic_add16# > > //////////////////////////////////////////////////////////////////////////// > // extern "C" int __rw_atomic_xchg32 (int *x, int y); > // > // Atomically assigns the 32-bit value y to *x and returns > // the original (before assignment) 32-bit value of *x. > //////////////////////////////////////////////////////////////////////////// > > .global __rw_atomic_xchg32# > .proc __rw_atomic_xchg32# > > __rw_atomic_xchg32: > > .prologue > .body > // .mfb > > addp4 r9 = 0, r32 // Needed to be able to dereference a 32 bit > pointer > ;; > xchg4 r8 = [r9], r33 > nop 0 > br.ret.sptk.many b0 > > .endp __rw_atomic_xchg32# > > //////////////////////////////////////////////////////////////////////////// > // extern "C" int __rw_atomic_add32 (int *x, int y); > // > // Atomically increments the 32-bit value *x by y and returns > // the new (after increment) 32-bit value of *x. > //////////////////////////////////////////////////////////////////////////// > > .global __rw_atomic_add32# > .proc __rw_atomic_add32# > > __rw_atomic_add32: > > .prologue > .body > // .mmb > mf > addp4 r9 = 0, r32 // Needed to be able to dereference a 32 bit > pointer > ;; > ld4.acq r15 = [r9] > nop 0 > ;; > .add32_busywait: > // .mmi > mov ar.ccv = r15 > add r8 = r15, r33 > mov r2 = r15 > ;; > // .mmb > nop 0 > cmpxchg4.acq r15 = [r9], r8, ar.ccv > nop 0 > ;; > // .mbb > cmp4.ne p8, p9 = r2, r15 > (p9) br.ret.dpnt.many rp > br .add32_busywait > > .endp __rw_atomic_add32# > ------------------------------------------------------------------- > End of src/atomic-ia64-32.s