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Subject [GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Date Sat, 16 May 2020 11:01:08 GMT

raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426143409



##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
##########
@@ -0,0 +1,194 @@
+/****************************************************************************************************
+ *  arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
+ *
+ *  Licensed to the Apache Software Foundation (ASF) under one or more
+ *  contributor license agreements.  See the NOTICE file distributed with
+ *  this work for additional information regarding copyright ownership.  The
+ *  ASF licenses this file to you under the Apache License, Version 2.0 (the
+ *  "License"); you may not use this file except in compliance with the
+ *  License.  You may obtain a copy of the License at
+ *
+ *    http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ *  License for the specific language governing permissions and limitations
+ *  under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* STM32G47xxx Address Blocks ***********************************************************************/
+
+#define STM32_CODE_BASE      0x00000000     /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE      0x20000000     /* 0x20000000-0x3fffffff: 512Mb sram block */
+#define STM32_PERIPH_BASE    0x40000000     /* 0x40000000-0x5fffffff: 512Mb peripheral block
*/
+#define STM32_FMC_BANK1      0x60000000     /* 0x60000000-0x6fffffff: 256Mb NOR/PSRMA/SRAM
*/
+                                            /* 0x70000000-0x7fffffff: Reserved */
+#define STM32_FMC_BANK3      0x80000000     /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
+#define STM32_QSPI_BANK1     0x90000000     /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
+
+#define STM32_FMC_QSPI_BASE  0xa0000000     /* 0xa0000000-0xbfffffff: 256Mb FMC and QUADSPI
registers */
+                                            /* 0xc0000000-0xdfffffff: Reserved */
+#define STM32_CORTEX_BASE    0xe0000000     /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block
*/
+
+#define STM32_REGION_MASK    Warning Not Cleared!  0xf0000000

Review comment:
        #define STM32_REGION_MASK    0xf0000000
   is OK.




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