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From dean gaudet <dgaudet-list-new-ht...@arctic.org>
Subject Re: plz vote on tagging current CVS as APACHE_2_0_19
Date Sat, 23 Jun 2001 17:36:55 GMT
On Thu, 21 Jun 2001, Bill Stoddard wrote:

> > This can be implemented just as well with the table implementation.  The
> > only thing you have to do is pad the scoreboard entry size to make it
> > equal to one cache line.
> >
> And waste more storage? I am not a CPU designer...how big are cache lines on the different
CPUs?
> Wouldn;t padding the storage just cause you to load your cache with memory that is NOT
USED at all?

cache line sizes vary, they're typically 32, 64, or 128 bytes these days.
32 bytes is the L1 line size on the p-iii family, the p4 family uses a
128-byte L1 line size.

so what happens when you have two processors banging on the same line is
that the memory accesses proceed at memory bus speed.  so instead of
taking 1 cycle for a read/write it takes 100s of cycles.

loading the cache with unused memory is a small penalty if it means you
can reap the benefits of exclusive access to that line of memory.

if you want to see some of this stuff for yourself grab
<ftp://ftp.bitkeeper.com/lmbench/lmbench-2beta3.tgz> and look at the
memory timings on your favourite system.

-dean


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