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Date: Fri, 6 Feb 2009 10:17:13 +0800
Message-ID: <9623c9a50902051817m2d878470j28ba3666a2c495cb@mail.gmail.com>
Subject: Re: discussion for H5022
From: Xiao-Feng Li <xiaofeng.li@gmail.com>
To: dev@harmony.apache.org
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Does newImmOpnd() generate 64bit imm?

Thanks,
xiaofeng

On Thu, Feb 5, 2009 at 4:20 PM, xiaoming gu <xiaoming.gu@gmail.com> wrote:
> I did some tests on 64-bit Windows and found sizeof(POINTER_SIZE_INT)=8. So
> I think no truncation happens. And I could NOT find the code mentioned in
> [1] and maybe it is because of some rollback. What's your opinion?
>
> Xiaoming
>
> [1] - https://issues.apache.org/jira/browse/HARMONY-5022
>
> On Mon, Nov 3, 2008 at 2:00 PM, xiaoming gu <xiaoming.gu@gmail.com> wrote:
>
>> So in 64-bit platform with compressed pointer, the base address for heap is
>> still 64-bit but the offset is 32-bit.
>>
>> Got it. Thanks. -Xiaoming
>>
>>
>> On Mon, Nov 3, 2008 at 12:21 PM, Xiao-Feng Li <xiaofeng.li@gmail.com>wrote:
>>
>>> Xiaoming, I think this work is only related with X86-64, the 64bit
>>> machine. In a 32bit platform, there is no such concept of 64-bit base
>>> address. In 64-bit platform with compressed pointer, we have a base
>>> address and a 32-bit offset for one pointer.
>>>
>>> Thanks,
>>> xiaofeng
>>>
>>> On Mon, Nov 3, 2008 at 11:52 AM, xiaoming gu <xiaoming.gu@gmail.com>
>>> wrote:
>>> > Hi, guys. I'm studying H5022 - incorrect codegeneration of compressed
>>> obj
>>> > arithmetics[1]. In my understanding, the problem is that current JIT
>>> casts
>>> > heap base address from 64-bit to 32-bit compulsorily in IA32 but that
>>> > address must be in 64-bit even in a 32-bit platform. If I catch the
>>> point of
>>> > this jira correctly, I'll try to delete the casts in
>>> > Ia32InstCodeSelector.cpp recently. Any comment? Thanks.
>>> >
>>> > Xiaoming
>>> >
>>> > [1] - https://issues.apache.org/jira/browse/HARMONY-5022
>>> >
>>>
>>>
>>>
>>> --
>>> http://xiao-feng.blogspot.com
>>>
>>
>>
>
>
> --
> China Runtime Technologies Lab,
> SSG/SSD/MRTC, Intel
>


-- 
Managed Runtime Technology Center, Intel