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Message-ID: <255079590809020030i42e638adocc0ef814b3c520ad@mail.gmail.com>
Date: Tue, 2 Sep 2008 15:30:10 +0800
From: "xiaoming gu" <xiaoming.gu@gmail.com>
To: dev@harmony.apache.org
Subject: Re: [jira] Created: (HARMONY-5965) [drlvm][jit]generate Mnemonic_LEA
 LIR for Op_Shladd HIR in IA32
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The work will be done in HIR2LIR pass. Thanks.

Xiaoming

On Tue, Sep 2, 2008 at 2:56 PM, Xiao-Feng Li <xiaofeng.li@gmail.com> wrote:

> On Tue, Sep 2, 2008 at 11:38 AM, Xiaoming Gu (JIRA) <jira@apache.org>
> wrote:
> > [drlvm][jit]generate Mnemonic_LEA LIR for Op_Shladd HIR in IA32
> > ---------------------------------------------------------------
> >
> >                 Key: HARMONY-5965
> >                 URL: https://issues.apache.org/jira/browse/HARMONY-5965
> >             Project: Harmony
> >          Issue Type: Improvement
> >          Components: DRLVM
> >            Reporter: Xiaoming Gu
> >
> >
> > In IA32 there is a quick (1 cycle) LEA instruction for loading effective
> address. The function of LEA is a combination of shift-left and addition.
> For example LEA dst, src, 2, 4 does dst=src<<2+4. It's usually used but not
> limited in element address calculation for array.
> >
> > In current Ia32InstCodeSelector.cpp, the function for translating
> Op_Shladd HIR generates shl and add. Since LEA has the same semantic, we
> could deploy it to improve performance.
>
> Thanks for the proposal. Which phase do you suggest to implement this
> optimization, IR lowering?
>
> Thanks,
> xiaofebg
>
> > --
> > This message is automatically generated by JIRA.
> > -
> > You can reply to this email to add a comment to the issue online.
> >
> >
>
>
>
> --
> http://xiao-feng.blogspot.com
>

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