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From "Xiao-Feng Li" <xiaofeng...@gmail.com>
Subject Re: [jira] Created: (HARMONY-5965) [drlvm][jit]generate Mnemonic_LEA LIR for Op_Shladd HIR in IA32
Date Tue, 02 Sep 2008 06:56:21 GMT
On Tue, Sep 2, 2008 at 11:38 AM, Xiaoming Gu (JIRA) <jira@apache.org> wrote:
> [drlvm][jit]generate Mnemonic_LEA LIR for Op_Shladd HIR in IA32
> ---------------------------------------------------------------
>
>                 Key: HARMONY-5965
>                 URL: https://issues.apache.org/jira/browse/HARMONY-5965
>             Project: Harmony
>          Issue Type: Improvement
>          Components: DRLVM
>            Reporter: Xiaoming Gu
>
>
> In IA32 there is a quick (1 cycle) LEA instruction for loading effective address. The
function of LEA is a combination of shift-left and addition. For example LEA dst, src, 2,
4 does dst=src<<2+4. It's usually used but not limited in element address calculation
for array.
>
> In current Ia32InstCodeSelector.cpp, the function for translating Op_Shladd HIR generates
shl and add. Since LEA has the same semantic, we could deploy it to improve performance.

Thanks for the proposal. Which phase do you suggest to implement this
optimization, IR lowering?

Thanks,
xiaofebg

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