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From "史成荣" <icyr...@gmail.com>
Subject Re: [drlvm][jitrino]
Date Sat, 15 Dec 2007 12:38:34 GMT
在07-12-15,Xiao-Feng Li <xiaofeng.li@gmail.com> 写道:
>
> On Dec 15, 2007 2:33 PM, 史成荣 <icyrong@gmail.com> wrote:
> > I still have 2 questions.
> >
> > First, I know in the Thread Manager, it is the
> > hythread_thin_monitor_try_enter method to aquire the mutex lock
> > and implement the *memory barrier.* But* *I looked into the code of this
> > method, didn't find any memory barrier operations(including the
> > apr_memory_rw_barrier() call and  cmpxchg operation) when it is the fat
> > lock. when aquiring the fat lock, it calls the
> hythread_monitor_try_enter
> > method. In the hythread_monitor_try_enter method* there isn't *memory
> > barrier operations, but has a call of the *hymutex_trylock* method. Does
> the
> > hymutex_trylock method also has barrier effect built-in?
> >
> > Second, when exit the synchoronized area, it should release the mutex
> lock
> > and flush the local memory to the main memory. But the
> > hythread_thin_monitor_exit method only release the mutex lock and I
> don't
> > find any flushing operation in hythread_thin_monitor_exit method.
>
>
> Chengrong, you have good questions. Your questions are related to
> processor memory model, or how to map Java memory model to the
> processor. For example, if the processor has sequential consistency,
> there is no need for any extra flushing operation because all the
> local memory operations enter the system memory hierarchy in order of
> issuing. X86 processors use "processor consistency" which is weaker
> than sequential consistency, so it has xfence instructions for the
> purpose.
>
> So to really understand the issues, you probably can read some
> materials on processor architecture, esp. the memory model part. There
> are chapters in "Computer architecture, a quantitative approach" or
> "Parallel architecture: a hardware/software interface". For a specific
> processor type, you can read its architecture manual to understand its
> behavior in SMP configuration. For example, "lock" prefix in X86
> processor has both barrier and flushing effects.


Do you mean it is OK that there is no flushing operation when exiting the
synchronized area? Or I missed the flushing opertions?

Thanks,
> xiaofeng
> >
> > I think there must be some mistakes of my idea, hoping for your advice.
> >
> >
> >
> > >  Thanks,
> > >  Chengrong
> > >
> > >
> > >
> > >
> >
>
>
>
> --
> http://xiao-feng.blogspot.com
>
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