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From "Mikhail Fursov" <mike.fur...@gmail.com>
Subject Re: [drlvm][jit]Generating block nodes in InstCodeSelector
Date Thu, 05 Apr 2007 12:49:41 GMT
On 4/5/07, Maksim Ananjev <maksim.ananjev@gmail.com> wrote:
>
> Hi!
>
> I have a question to jit gurus on LIR generation.
>
> I've implemented an instruction in HIR that should contain three
> consecutive check operations. So, I try to select LIR code out of it
> in Code Selector. The obvious low-level implementation of my
> instruction is three consecutive branch operations.
>
> However, there is a problem: control flow graph must have only on
> branch operation per node.
>
> Is there a way to generate nodes correctly in InstCodeSelector? And
> what should be done afterwards to fix them in control flow graph?
>
>
Maxim,
I see the following solution and think this solution is good for you:
1) Transform your instruction into new PseudoInst successor in CodeSelector
2) Write additional IR transformation pass to expand your pseudo insts into
real insts/sub graphs.

Doing this you will avoid limitations of  CodeSelector pass architecture and
will not complicate its logic.




-- 
Mikhail Fursov

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