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From "Rana Dasgupta" <rdasg...@gmail.com>
Subject Re: [general] What platforms do we support?
Date Wed, 04 Apr 2007 20:48:51 GMT
On 4/4/07, Gregory Shimansky <gshimansky@gmail.com> wrote:
> On Wednesday 04 April 2007 23:33 Rana Dasgupta wrote:
> > On 4/4/07, Mikhail Fursov <mike.fursov@gmail.com> wrote:
> > > On 4/4/07, Alexey Petrenko <alexey.a.petrenko@gmail.com> wrote:
> > > > 2007/4/4, Gregory Shimansky <gshimansky@gmail.com>:
> > > > > > > I would like to see these modifications. I wonder what
you've
> > > > > > > done in
> > > > >
> > > > > port/src/thread/linux/apr_thread_ext.c and vmcore/include/atomics.h.
> > > > > They contain mfence and sfence instructions in inline assembly which
> > > > > have to be changed to something else on P3.
> >
> > MemoryWriteBarrier() etc. should be no-ops on PIII. x86 is already
> > strongly ordered for writes ?
>
> What about MemoryReadWriteBarrier()? If you know, what kind of code should be
> used for this in P3?

One of the compiler guys can confirm this. But I don't believe that
you need to worry about any of the fence instructions fence on any of
the PIII, PIV genuine intel procs unless you are using streaming mode
( SIMD ) instructions which are weakly ordered.

>
> --
> Gregory
>

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