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From "Rana Dasgupta" <rdasg...@gmail.com>
Subject Re: [drlvm] tests failing on linux (Ubuntu 7.04-dev) with Quad Xeon P3
Date Sat, 31 Mar 2007 17:58:24 GMT
On 3/31/07, Gregory Shimansky <gshimansky@gmail.com> wrote:
> Nathan Beyer wrote:
> > On 3/30/07, Nathan Beyer <ndbeyer@apache.org> wrote:
> > Okay, I'm trying that out now. Can the JIT be a little smarter and not
> >use instructions that aren't available? We certainly can't limit
> > available platforms to P4 or newer.
> I hope JIT gurus can answer this. I know that JIT can use x87 stack
> instead of SSE for floating point, but other P4 specific instructions
> may still be present in the code. I know at least one place in DRLVM
> where mfence, sfence and lfence are used explicitly in inline assembly.
We have had these discussions before when discussing JIT plans etc. We
did discuss that the floating point operations generated by jitrino,
as contributed, uses sse2 and that porting to the x87 stack was a TBD.

We also stated in these discussions that the "minimum machine model"
was a P4, which implies that it was an assumption that P4 instructions
were available  and P4 specific optimization patterns could be used. I
am sure that these discussions are there in the archives.

Nathan, would it be at all possible for you to move to a P4 machine? I
am not aware of any JIT plan to be P3 compatible, maybe Pavel or
Mikhail Fursov can comment.


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