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From "Ivan Volosyuk" <ivan.volos...@gmail.com>
Subject Re: [drlvm] Class unloading support - tested one approach
Date Thu, 09 Nov 2006 18:37:15 GMT
On 11/9/06, Etienne Gagnon <egagnon@sablevm.org> wrote:
> Ivan Volosyuk wrote:
> > We will get rid of false sharing. That's true. But it still be quite
> > expensive to write those '1' values, because of ping-ponging of the
> > cache line between processors. I see only one solution to this: use
> > separate mark bits in vtable per GC thread which should reside in
> > different cache lines and different from that word containing gcmap
> > pointer.
> The only thing that a GC thread does is write "1" in this slot; it never
> writes "0".  So, it is not very important in what order (or even "when")
> this word is finally commited to main memory.  As long as there is some
> barrier before the "end of epoch collection" insuring that all
> processors cache write buffers are commited to memory before tracing
> vtables (or gc maps).
> You don't need memory coherency on write-without-read. :-)

I don't speak about memory coherency, I speak about bus load with
useless memory traffic between processors and poor CPU cache usage.

Intel Enterprise Solutions Software Division

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