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From "Xiao-Feng Li" <xiaofeng...@gmail.com>
Subject Re: [DRLVM] (JIRA 1580) write barrier implementation for JET
Date Wed, 27 Sep 2006 05:23:03 GMT
Thanks. Yes, this is supposed to be review by JIT person. On the other
hand, if JIT person has better solution, GCv5 would like to use.
Anyway we hope write barrier is to be functioning in the DRLVM soon.

Thanks,
xiaofeng

On 9/27/06, Weldon Washburn <weldonwjw@gmail.com> wrote:
> It would probably be best if a JIT person committed this patch.  Maybe
> Stephan Mishura?
>
> If its not committed soon, bug me and I will do it.
>
>
> On 9/26/06, Xiao-Feng Li <xiaofeng.li@gmail.com> wrote:
> >
> > Hi, the patch attached in JIRA 1580 (submitted by YuNan) is a write
> > barrier implementation for JET that GCv5 is going to use (it doesn't
> > impact anything else). It would be great if some commiter can help to
> > review and commit it. Thanks. -xiaofeng
> >
> > http://issues.apache.org/jira/browse/HARMONY-1580?page=all
> >
> > The patch is against revision revision 442796.
> >
> > Repeat the desciption of the patch:
> > "Attached patch is an implementation of write barrier for JET compiler
> > of DRLVM. The patch lets JET to call "gc_requires_barriers()" of GC to
> > determine if it needs to insert the write barrier code into the jitted
> > code, so it doesn't impact current DRLVM/GC at all. It calls
> > gc_heap_slot_write_ref( ) of GC module, which takes three parameters.
> > The signature is "void gc_heap_slot_write_ref (Managed_Object_Handle
> > p_obj_holding_ref,Managed_Object_Handle *p_slot, Managed_Object_Handle
> > p_target)".
> >
> > The patch is based on revision 442796. We hope it can be committed to
> > Harmony soon because GCv5 will be depending on it. We don't use
> > existing getaddress__gc_write_barrier_fastcall () in DRLVM because it
> > only remembers object rather than the slot, and the name is not
> > descriptive. But we may use it later. Thanks."
> >
> > ---------------------------------------------------------------------
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> >
> >
>
>
> --
> Weldon Washburn
> Intel Middleware Products Division
>
>

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