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From "Weldon Washburn" <weldon...@gmail.com>
Subject [DRLVM][VM] set_hash_bits() in vmcore/src/thread/mon_enter_exit.cpp -- is it a bug or a feature?
Date Mon, 28 Aug 2006 15:32:52 GMT
While porting MMTk to harmony/drlvm, I hit an integration problem.  It
could even be a bug.  set_hash_bits() assumes the least significant
bit is zero.  Assuming that the LSB can be "owned" by the garbage
collector for its purposes, set_hash_bits() will fail if the GC sets
this bit to one.  Somehow I think the code should read the target
location, create the intended bit pattern before attempting to do the
atomic compare and swap.  Currently the code assume the target CAS
location holds zero.

SInce I am working only in single thread right now, I hacked around
the problem with the below.  Thoughts?


C:\t_harmony\drlvm\trunk\vm\vmcore\src\thread>svn diff mon_enter_exit.cpp
Index: mon_enter_exit.cpp
===================================================================
--- mon_enter_exit.cpp  (revision 425482)
+++ mon_enter_exit.cpp  (working copy)
@@ -368,7 +368,12 @@
         hb = (23 & HASH_MASK);  // NO hash = zero allowed, thus hard map hb = 0
 to a fixed prime number

     // don't care if the cmpxchg fails -- just means someone else already set t
he hash
-    port_atomic_cas8(P_HASH_CONTENTION(p_obj),hb, 0);
+    //port_atomic_cas8(P_HASH_CONTENTION(p_obj),hb, 0);
+    unsigned char lsb = *P_HASH_CONTENTION(p_obj);
+    lsb = lsb & 0x01;  //wjw need to keep the LSB, its used by MMTk Garbage Col
lector
+    hb = hb | lsb;
+    if ( (*P_HASH_CONTENTION(p_obj) & HASH_MASK) == 0 ) // wjw non-atomic hack
for now
+        *P_HASH_CONTENTION(p_obj) = hb;
 }




-- 
Weldon Washburn
Intel Middleware Products Division

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