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From "Ivan Volosyuk" <ivan.volos...@gmail.com>
Subject Re: [DRLVM][VM] -- which header bits are available for GC mark and GC forwarding use?
Date Fri, 25 Aug 2006 09:10:42 GMT
Weldon, look at the patch in http://issues.apache.org/jira/browse/HARMONY-1269.
I have already done this work. After the patch you have whole lowest
byte + 2 bits in the second byte for GC use; in expense of
implementing hashcode by GC.

In my understanding the hashcode can be reduced to 2 status bits in object info:
  00. hashcode is not set
  01. hashcode is set (hashcode is the address of object)
  11. hashcode is set and object is moved (hashcode is no longer the
address of object)

This layout require assistance from GC (which is missing in GC_V4).

I suggest using interface function: gc_get_hashcode() in GC-to-VM
interface which will know exactly the layout of bits in the lowest
byte of hashcode and will do all the needed actions depending on the
GC implementation.

On 8/25/06, Weldon Washburn <weldonwjw@gmail.com> wrote:
> On 8/24/06, Salikh Zakirov <Salikh.Zakirov@intel.com> wrote:
> > In any way, currently there is no single header file in the system,
> > which would describe the object structure. Rather, DRLVM uses some
> > static assumptions about object header, which are not enforced by any
> > common include file. This would be a nice thing to solve...
> Good point.  There needs to be a discussion on harmony-dev regarding
> how the object header bits are "sliced and diced".  From talking to
> the MMTk guys (Steve Blackburn) it seems MMTk wants to have one byte
> of object header for private use.  Its unclear to me if this will be a
> performance problem for a product JVM.  I think the hashCode can be
> reduced to one bit plus the object's current address at first
> HashCode() invocation.  I'd put this hash bit in the GC byte.  And
> make the GC byte the lowest byte in the header word.  The remaining
> 3bytes could be used for fat/thin locks.  Are there any remaining
> fields unaccounted for?  Thoughts?
> --
> Weldon Washburn
> Intel Middleware Products Division

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