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From chunr...@apache.org
Subject svn commit: r706374 [2/2] - in /harmony/enhanced/drlvm/trunk/vm: jitrino/src/codegenerator/ia32/ jitrino/src/jet/ jitrino/src/optimizer/ jitrino/src/shared/ port/src/encoder/ia32_em64t/ vmcore/src/lil/em64t/ vmcore/src/lil/ia32/ vmcore/src/thread/helpe...
Date Mon, 20 Oct 2008 19:18:03 GMT
Modified: harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h?rev=706374&r1=706373&r2=706374&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h (original)
+++ harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h Mon Oct 20 12:18:01 2008
@@ -136,111 +136,94 @@
 #define rw          OpcodeByteKind_rw
 #define rd          OpcodeByteKind_rd
 
-#define AL          {OpndKind_GPReg, OpndSize_8, OpndExt_Any, RegName_AL}
-#define AH          {OpndKind_GPReg, OpndSize_8, OpndExt_Any, RegName_AH}
-#define AX          {OpndKind_GPReg, OpndSize_16, OpndExt_Any, RegName_AX}
-#define EAX         {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_EAX}
+#define AL          {OpndKind_GPReg, OpndSize_8, RegName_AL}
+#define AH          {OpndKind_GPReg, OpndSize_8, RegName_AH}
+#define AX          {OpndKind_GPReg, OpndSize_16, RegName_AX}
+#define EAX         {OpndKind_GPReg, OpndSize_32, RegName_EAX}
 #ifdef _EM64T_
-    #define RAX     {OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RAX }
+    #define RAX     {OpndKind_GPReg, OpndSize_64, RegName_RAX }
 #endif
 
-#define CL          {OpndKind_GPReg, OpndSize_8, OpndExt_Any, RegName_CL}
-#define ECX         {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_ECX}
+#define CL          {OpndKind_GPReg, OpndSize_8, RegName_CL}
+#define ECX         {OpndKind_GPReg, OpndSize_32, RegName_ECX}
 #ifdef _EM64T_
-    #define RCX         {OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RCX}
+    #define RCX         {OpndKind_GPReg, OpndSize_64, RegName_RCX}
 #endif
 
-#define DX          {OpndKind_GPReg, OpndSize_16, OpndExt_Any, RegName_DX}
-#define EDX         {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_EDX}
+#define DX          {OpndKind_GPReg, OpndSize_16, RegName_DX}
+#define EDX         {OpndKind_GPReg, OpndSize_32, RegName_EDX}
 #ifdef _EM64T_
-    #define RDX     { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RDX }
+    #define RDX     { OpndKind_GPReg, OpndSize_64, RegName_RDX }
 #endif
 
-#define ESI         {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_ESI}
+#define ESI         {OpndKind_GPReg, OpndSize_32, RegName_ESI}
 #ifdef _EM64T_
-    #define RSI     { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RSI }
+    #define RSI     { OpndKind_GPReg, OpndSize_64, RegName_RSI }
 #endif
 
-#define EDI         {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_EDI}
+#define EDI         {OpndKind_GPReg, OpndSize_32, RegName_EDI}
 #ifdef _EM64T_
-    #define RDI     { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RDI }
+    #define RDI     { OpndKind_GPReg, OpndSize_64, RegName_RDI }
 #endif
 
-#define r8          {OpndKind_GPReg, OpndSize_8, OpndExt_Any, RegName_Null}
-#define r16         {OpndKind_GPReg, OpndSize_16, OpndExt_Any, RegName_Null}
-#define r32         {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_Null}
+#define r8          {OpndKind_GPReg, OpndSize_8, RegName_Null}
+#define r16         {OpndKind_GPReg, OpndSize_16, RegName_Null}
+#define r32         {OpndKind_GPReg, OpndSize_32, RegName_Null}
 #ifdef _EM64T_
-    #define r64     { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_Null }
+    #define r64     { OpndKind_GPReg, OpndSize_64, RegName_Null }
 #endif
 
-#define r_m8        {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_8, OpndExt_Any, RegName_Null}
-#define r_m16       {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_16, OpndExt_Any, RegName_Null}
-#define r_m32       {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_32, OpndExt_Any, RegName_Null}
-
-#define r_m8s        {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_8, OpndExt_Signed, RegName_Null}
-#define r_m16s       {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_16, OpndExt_Signed, RegName_Null}
-#define r_m32s       {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_32, OpndExt_Signed, RegName_Null}
-
-#define r_m8u        {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_8, OpndExt_Zero, RegName_Null}
-#define r_m16u       {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_16, OpndExt_Zero, RegName_Null}
-#define r_m32u       {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_32, OpndExt_Zero, RegName_Null}
+#define r_m8        {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_8, RegName_Null}
+#define r_m16       {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_16, RegName_Null}
+#define r_m32       {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_32, RegName_Null}
 
 //'m' was only used in LEA mnemonic, but is replaced with 
 // set of exact sizes. See more comments for LEA instruction in TheTable.
 //#define m           {OpndKind_Mem, OpndSize_Null, RegName_Null}
-#define m8          {OpndKind_Mem, OpndSize_8, OpndExt_Any, RegName_Null}
-#define m16         {OpndKind_Mem, OpndSize_16, OpndExt_Any, RegName_Null}
-#define m32         {OpndKind_Mem, OpndSize_32, OpndExt_Any, RegName_Null}
-#define m64         {OpndKind_Mem, OpndSize_64, OpndExt_Any, RegName_Null}
+#define m8          {OpndKind_Mem, OpndSize_8, RegName_Null}
+#define m16         {OpndKind_Mem, OpndSize_16, RegName_Null}
+#define m32         {OpndKind_Mem, OpndSize_32, RegName_Null}
+#define m64         {OpndKind_Mem, OpndSize_64, RegName_Null}
 #ifdef _EM64T_
-    #define r_m64   { (OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_64, OpndExt_Any, RegName_Null }
+    #define r_m64   { (OpndKind)(OpndKind_GPReg|OpndKind_Mem),      OpndSize_64, RegName_Null }
 #endif
 
-#define imm8        {OpndKind_Imm, OpndSize_8, OpndExt_Any, RegName_Null}
-#define imm16       {OpndKind_Imm, OpndSize_16, OpndExt_Any, RegName_Null}
-#define imm32       {OpndKind_Imm, OpndSize_32, OpndExt_Any, RegName_Null}
-
-#define imm8s        {OpndKind_Imm, OpndSize_8, OpndExt_Signed, RegName_Null}
-#define imm16s       {OpndKind_Imm, OpndSize_16, OpndExt_Signed, RegName_Null}
-#define imm32s       {OpndKind_Imm, OpndSize_32, OpndExt_Signed, RegName_Null}
-
-#define imm8u        {OpndKind_Imm, OpndSize_8, OpndExt_Zero, RegName_Null}
-#define imm16u       {OpndKind_Imm, OpndSize_16, OpndExt_Zero, RegName_Null}
-#define imm32u       {OpndKind_Imm, OpndSize_32, OpndExt_Zero, RegName_Null}
-
+#define imm8        {OpndKind_Imm, OpndSize_8, RegName_Null}
+#define imm16       {OpndKind_Imm, OpndSize_16, RegName_Null}
+#define imm32       {OpndKind_Imm, OpndSize_32, RegName_Null}
 #ifdef _EM64T_
-    #define imm64   {OpndKind_Imm, OpndSize_64, OpndExt_Any, RegName_Null }
+    #define imm64   {OpndKind_Imm, OpndSize_64, RegName_Null }
 #endif
 
 //FIXME: moff-s are in fact memory refs, but presented as immediate.
 // Need to specify this in OpndDesc.
-#define moff8        {OpndKind_Imm, OpndSize_32, OpndExt_Any, RegName_Null}
-#define moff16       {OpndKind_Imm, OpndSize_32, OpndExt_Any, RegName_Null}
-#define moff32       {OpndKind_Imm, OpndSize_32, OpndExt_Any, RegName_Null}
+#define moff8        {OpndKind_Imm, OpndSize_32, RegName_Null}
+#define moff16       {OpndKind_Imm, OpndSize_32, RegName_Null}
+#define moff32       {OpndKind_Imm, OpndSize_32, RegName_Null}
 #ifdef _EM64T_
-    #define moff64       {OpndKind_Imm, OpndSize_64, OpndExt_Any, RegName_Null}
+    #define moff64       {OpndKind_Imm, OpndSize_64, RegName_Null}
 #endif
 
 
-#define rel8        {OpndKind_Imm, OpndSize_8, OpndExt_Any, RegName_Null}
-#define rel16       {OpndKind_Imm, OpndSize_16, OpndExt_Any, RegName_Null}
-#define rel32       {OpndKind_Imm, OpndSize_32, OpndExt_Any, RegName_Null}
+#define rel8        {OpndKind_Imm, OpndSize_8, RegName_Null}
+#define rel16       {OpndKind_Imm, OpndSize_16, RegName_Null}
+#define rel32       {OpndKind_Imm, OpndSize_32, RegName_Null}
 
-#define mm64        {OpndKind_MMXReg, OpndSize_64, OpndExt_Any, RegName_Null}
-#define mm_m64      {(OpndKind)(OpndKind_MMXReg|OpndKind_Mem), OpndSize_64, OpndExt_Any, RegName_Null} 
+#define mm64        {OpndKind_MMXReg, OpndSize_64, RegName_Null}
+#define mm_m64      {(OpndKind)(OpndKind_MMXReg|OpndKind_Mem), OpndSize_64, RegName_Null} 
 
-#define xmm64       {OpndKind_XMMReg, OpndSize_64, OpndExt_Any, RegName_Null}
-#define xmm_m64     {(OpndKind)(OpndKind_XMMReg|OpndKind_Mem), OpndSize_64, OpndExt_Any, RegName_Null} 
+#define xmm64       {OpndKind_XMMReg, OpndSize_64, RegName_Null}
+#define xmm_m64     {(OpndKind)(OpndKind_XMMReg|OpndKind_Mem), OpndSize_64, RegName_Null} 
 
-#define xmm32       {OpndKind_XMMReg, OpndSize_32, OpndExt_Any, RegName_Null}
-#define xmm_m32     {(OpndKind)(OpndKind_XMMReg|OpndKind_Mem), OpndSize_32, OpndExt_Any, RegName_Null}
+#define xmm32       {OpndKind_XMMReg, OpndSize_32, RegName_Null}
+#define xmm_m32     {(OpndKind)(OpndKind_XMMReg|OpndKind_Mem), OpndSize_32, RegName_Null}
 
-#define FP0S        {OpndKind_FPReg, OpndSize_32, OpndExt_Any, RegName_FP0S}
-#define FP0D        {OpndKind_FPReg, OpndSize_64, OpndExt_Any, RegName_FP0D}
-#define FP1S        {OpndKind_FPReg, OpndSize_32, OpndExt_Any, RegName_FP1S}
-#define FP1D        {OpndKind_FPReg, OpndSize_64, OpndExt_Any, RegName_FP1D}
-#define fp32        {OpndKind_FPReg, OpndSize_32, OpndExt_Any, RegName_Null}
-#define fp64        {OpndKind_FPReg, OpndSize_64, OpndExt_Any, RegName_Null}
+#define FP0S        {OpndKind_FPReg, OpndSize_32, RegName_FP0S}
+#define FP0D        {OpndKind_FPReg, OpndSize_64, RegName_FP0D}
+#define FP1S        {OpndKind_FPReg, OpndSize_32, RegName_FP1S}
+#define FP1D        {OpndKind_FPReg, OpndSize_64, RegName_FP1D}
+#define fp32        {OpndKind_FPReg, OpndSize_32, RegName_Null}
+#define fp64        {OpndKind_FPReg, OpndSize_64, RegName_Null}
 
 #ifdef _EM64T_
     #define io      OpcodeByteKind_io

Modified: harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp?rev=706374&r1=706373&r2=706374&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp Mon Oct 20 12:18:01 2008
@@ -328,7 +328,7 @@
 BEGIN_MNEMONIC(LAHF, MF_USES_FLAGS, D)
 BEGIN_OPCODES()
 // TheManual says it's not always supported in em64t mode, thus excluding it
-    {OpcodeInfo::ia32,    {0x9F},  {EAX}, D },
+    {OpcodeInfo::ia32,    {0x9F},         {EAX}, D },
 END_OPCODES()
 END_MNEMONIC()
 //
@@ -348,28 +348,28 @@
     {OpcodeInfo::decoder,   {opcode_starts_from + 4, ib},           {AL,    imm8},  DU_U },\
     {OpcodeInfo::decoder,   {Size16, opcode_starts_from + 5, iw},   {AX,    imm16}, DU_U },\
     {OpcodeInfo::decoder,   {opcode_starts_from + 5, id},           {EAX,   imm32}, DU_U },\
-    {OpcodeInfo::decoder64, {REX_W, opcode_starts_from+5, id},      {RAX,   imm32s},DU_U },\
+    {OpcodeInfo::decoder64, {REX_W, opcode_starts_from+5, id},      {RAX,   imm32}, DU_U },\
 \
-    {OpcodeInfo::all,       {0x80, opc_ext, ib},          {r_m8,  imm8},    def_use },\
-    {OpcodeInfo::all,       {Size16, 0x81, opc_ext, iw},  {r_m16, imm16},   def_use },\
-    {OpcodeInfo::all,       {0x81, opc_ext, id},          {r_m32, imm32},   def_use },\
-    {OpcodeInfo::em64t,     {REX_W, 0x81, opc_ext, id},   {r_m64, imm32s},  def_use },\
+    {OpcodeInfo::all,     {0x80, opc_ext, ib},          {r_m8,  imm8},  def_use },\
+    {OpcodeInfo::all,     {Size16, 0x81, opc_ext, iw},  {r_m16, imm16}, def_use },\
+    {OpcodeInfo::all,     {0x81, opc_ext, id},          {r_m32, imm32}, def_use },\
+    {OpcodeInfo::em64t,   {REX_W, 0x81, opc_ext, id},   {r_m64, imm32}, def_use },\
 \
-    {OpcodeInfo::all,       {Size16, 0x83, opc_ext, ib},  {r_m16, imm8s},   def_use },\
-    {OpcodeInfo::all,       {0x83, opc_ext, ib},          {r_m32, imm8s},   def_use },\
-    {OpcodeInfo::em64t,     {REX_W, 0x83, opc_ext, ib},   {r_m64, imm8s},   def_use },\
+    {OpcodeInfo::all,     {Size16, 0x83, opc_ext, ib},  {r_m16, imm8},  def_use },\
+    {OpcodeInfo::all,     {0x83, opc_ext, ib},          {r_m32, imm8},  def_use },\
+    {OpcodeInfo::em64t,   {REX_W, 0x83, opc_ext, ib},   {r_m64, imm8},  def_use },\
 \
-    {OpcodeInfo::all,       {first_opcode,  _r},          {r_m8,  r8},      def_use },\
+    {OpcodeInfo::all,     {first_opcode,  _r},          {r_m8,  r8},    def_use },\
 \
-    {OpcodeInfo::all,       {Size16, opcode_starts_from+1,  _r},  {r_m16, r16},   def_use },\
-    {OpcodeInfo::all,       {opcode_starts_from+1,  _r},  {r_m32, r32},   def_use },\
-    {OpcodeInfo::em64t,     {REX_W, opcode_starts_from+1, _r},    {r_m64, r64},   def_use },\
+    {OpcodeInfo::all,     {Size16, opcode_starts_from+1,  _r},  {r_m16, r16},   def_use },\
+    {OpcodeInfo::all,     {opcode_starts_from+1,  _r},  {r_m32, r32},   def_use },\
+    {OpcodeInfo::em64t,   {REX_W, opcode_starts_from+1, _r},    {r_m64, r64},   def_use },\
 \
-    {OpcodeInfo::all,       {opcode_starts_from+2,  _r},  {r8,    r_m8},  def_use },\
+    {OpcodeInfo::all,     {opcode_starts_from+2,  _r},  {r8,    r_m8},  def_use },\
 \
-    {OpcodeInfo::all,       {Size16, opcode_starts_from+3,  _r},  {r16,   r_m16}, def_use },\
-    {OpcodeInfo::all,       {opcode_starts_from+3,  _r},  {r32,   r_m32}, def_use },\
-    {OpcodeInfo::em64t,     {REX_W, opcode_starts_from+3, _r},    {r64,   r_m64}, def_use },
+    {OpcodeInfo::all,     {Size16, opcode_starts_from+3,  _r},  {r16,   r_m16}, def_use },\
+    {OpcodeInfo::all,     {opcode_starts_from+3,  _r},  {r32,   r_m32}, def_use },\
+    {OpcodeInfo::em64t,   {REX_W, opcode_starts_from+3, _r},    {r64,   r_m64}, def_use },
 
 BEGIN_MNEMONIC(ADD, MF_AFFECTS_FLAGS|MF_SYMMETRIC, DU_U)
 BEGIN_OPCODES()
@@ -423,16 +423,16 @@
 
 BEGIN_MNEMONIC(CMPXCHG, MF_AFFECTS_FLAGS, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x0F, 0xB0, _r},           {r_m8, r8, AL},     DU_DU_DU },
-    {OpcodeInfo::all,   {Size16, 0x0F, 0xB1, _r},   {r_m16, r16, AX},   DU_DU_DU },
-    {OpcodeInfo::all,   {0x0F, 0xB1, _r},           {r_m32, r32, EAX},  DU_DU_DU},
-    {OpcodeInfo::em64t, {REX_W, 0x0F, 0xB1, _r},    {r_m64, r64, RAX},  DU_DU_DU },
+    {OpcodeInfo::all, {0x0F, 0xB0, _r},         {r_m8, r8, AL},     DU_DU_DU },
+    {OpcodeInfo::all, {Size16, 0x0F, 0xB1, _r}, {r_m16, r16, AX},   DU_DU_DU },
+    {OpcodeInfo::all, {0x0F, 0xB1, _r},         {r_m32, r32, EAX},   DU_DU_DU},
+    {OpcodeInfo::em64t, {REX_W, 0x0F, 0xB1, _r},{r_m64, r64, RAX},   DU_DU_DU },
 END_OPCODES()
 END_MNEMONIC()
  
 BEGIN_MNEMONIC(CMPXCHG8B, MF_AFFECTS_FLAGS, D)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x0F, 0xC7, _1},         {m64},     DU },
+    {OpcodeInfo::all, {0x0F, 0xC7, _1},         {m64},     DU },
 END_OPCODES()
 END_MNEMONIC()
  
@@ -442,50 +442,50 @@
 //
 BEGIN_MNEMONIC(ADDSD, MF_NONE, DU_U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF2, 0x0F, 0x58, _r},   {xmm64, xmm_m64},   DU_U},
+    {OpcodeInfo::all, {0xF2, 0x0F, 0x58, _r},   {xmm64, xmm_m64},   DU_U},
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(ADDSS, MF_NONE, DU_U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF3, 0x0F, 0x58, _r},   {xmm32, xmm_m32},   DU_U},
+    {OpcodeInfo::all, {0xF3, 0x0F, 0x58, _r},   {xmm32, xmm_m32},   DU_U},
 END_OPCODES()
 END_MNEMONIC()
 
 
 BEGIN_MNEMONIC(BSF, MF_AFFECTS_FLAGS, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x0F, 0xBC},   {r32, r_m32},   D_U},
+{OpcodeInfo::all, {0x0F, 0xBC},   {r32, r_m32},   D_U},
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(BSR, MF_AFFECTS_FLAGS, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x0F, 0xBD},   {r32, r_m32},   D_U},
+    {OpcodeInfo::all, {0x0F, 0xBD},   {r32, r_m32},   D_U},
 END_OPCODES()
 END_MNEMONIC()
 
 
 BEGIN_MNEMONIC(CALL, MF_NONE, U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xE8, cd},        {rel32},     U },
-    {OpcodeInfo::ia32,  {0xFF, _2},        {r_m32},     U },
-    {OpcodeInfo::em64t, {0xFF, _2},        {r_m64},     U },
+    {OpcodeInfo::all,     {0xE8, cd},        {rel32},     U },
+    {OpcodeInfo::ia32,    {0xFF, _2},        {r_m32},     U },
+    {OpcodeInfo::em64t,   {0xFF, _2},        {r_m64},     U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(CMC, MF_USES_FLAGS|MF_AFFECTS_FLAGS, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::decoder,   {0xF5},         {},     N },
+    {OpcodeInfo::decoder,     {0xF5},         {},     N },
 END_OPCODES()
 END_MNEMONIC()
 
 //TODO: Workaround. Actually, it's D_DU, but Jitrino's CG thinks it's D_U
 BEGIN_MNEMONIC(CDQ, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,       {0x99},         {DX, AX},       D_U },
-    {OpcodeInfo::all,       {0x99},         {EDX, EAX},     D_U },
-    {OpcodeInfo::em64t,     {REX_W, 0x99},  {RDX, RAX},     D_U },
+    {OpcodeInfo::all,     {0x99},         {DX, AX},       D_U },
+    {OpcodeInfo::all,     {0x99},         {EDX, EAX},     D_U },
+    {OpcodeInfo::em64t,   {REX_W, 0x99},  {RDX, RAX},     D_U },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -524,62 +524,62 @@
 // double -> float
 BEGIN_MNEMONIC(CVTSD2SS, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF2, 0x0F, 0x5A, _r},   {xmm32, xmm_m64}, D_U },
+    {OpcodeInfo::all,     {0xF2, 0x0F, 0x5A, _r},   {xmm32, xmm_m64}, D_U },
 END_OPCODES()
 END_MNEMONIC()
 
 // double -> I_32
 BEGIN_MNEMONIC(CVTSD2SI, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF2, 0x0F, 0x2D, _r},         {r32, xmm_m64}, D_U },
-    {OpcodeInfo::em64t, {REX_W, 0xF2, 0x0F, 0x2D, _r},  {r64, xmm_m64}, D_U },
+    {OpcodeInfo::all,     {0xF2, 0x0F, 0x2D, _r},      {r32, xmm_m64}, D_U },
+    {OpcodeInfo::em64t, {REX_W, 0xF2, 0x0F, 0x2D, _r}, {r64, xmm_m64}, D_U },
 END_OPCODES()
 END_MNEMONIC()
 
 // double [truncated] -> I_32
 BEGIN_MNEMONIC(CVTTSD2SI, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF2, 0x0F, 0x2C, _r},         {r32, xmm_m64}, D_U },
-    {OpcodeInfo::em64t, {REX_W, 0xF2, 0x0F, 0x2C, _r},  {r64, xmm_m64}, D_U },
+    {OpcodeInfo::all,     {0xF2, 0x0F, 0x2C, _r},      {r32, xmm_m64}, D_U },
+    {OpcodeInfo::em64t, {REX_W, 0xF2, 0x0F, 0x2C, _r}, {r64, xmm_m64}, D_U },
 END_OPCODES()
 END_MNEMONIC()
 
 // float -> double
 BEGIN_MNEMONIC(CVTSS2SD, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF3, 0x0F, 0x5A, _r},         {xmm64, xmm_m32}, D_U },
+    {OpcodeInfo::all,     {0xF3, 0x0F, 0x5A, _r},   {xmm64, xmm_m32}, D_U },
 END_OPCODES()
 END_MNEMONIC()
 
 // float -> I_32
 BEGIN_MNEMONIC(CVTSS2SI, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF3, 0x0F, 0x2D, _r},         {r32, xmm_m32}, D_U},
-    {OpcodeInfo::em64t, {REX_W, 0xF3, 0x0F, 0x2D, _r},  {r64, xmm_m32}, D_U},
+    {OpcodeInfo::all,     {0xF3, 0x0F, 0x2D, _r},         {r32, xmm_m32}, D_U},
+    {OpcodeInfo::em64t,   {REX_W, 0xF3, 0x0F, 0x2D, _r},  {r64, xmm_m32}, D_U},
 END_OPCODES()
 END_MNEMONIC()
 
 // float [truncated] -> I_32
 BEGIN_MNEMONIC(CVTTSS2SI, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF3, 0x0F, 0x2C, _r},         {r32, xmm_m32}, D_U},
-    {OpcodeInfo::em64t, {REX_W, 0xF3, 0x0F, 0x2C, _r},  {r64, xmm_m32}, D_U},
+    {OpcodeInfo::all,     {0xF3, 0x0F, 0x2C, _r},         {r32, xmm_m32}, D_U},
+    {OpcodeInfo::em64t,   {REX_W, 0xF3, 0x0F, 0x2C, _r},  {r64, xmm_m32}, D_U},
 END_OPCODES()
 END_MNEMONIC()
 
 // I_32 -> double
 BEGIN_MNEMONIC(CVTSI2SD, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF2, 0x0F, 0x2A, _r},         {xmm64, r_m32}, D_U},
-    {OpcodeInfo::em64t, {REX_W, 0xF2, 0x0F, 0x2A, _r},  {xmm64, r_m64}, D_U},
+    {OpcodeInfo::all,     {0xF2, 0x0F, 0x2A, _r},         {xmm64, r_m32}, D_U},
+    {OpcodeInfo::em64t, {REX_W, 0xF2, 0x0F, 0x2A, _r},    {xmm64, r_m64}, D_U},
 END_OPCODES()
 END_MNEMONIC()
 
 // I_32 -> float
 BEGIN_MNEMONIC(CVTSI2SS, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF3, 0x0F, 0x2A, _r},         {xmm32, r_m32}, D_U},
-    {OpcodeInfo::em64t, {REX_W, 0xF3, 0x0F, 0x2A, _r},  {xmm32, r_m64}, D_U},
+    {OpcodeInfo::all,     {0xF3, 0x0F, 0x2A, _r},         {xmm32, r_m32}, D_U},
+    {OpcodeInfo::em64t,   {REX_W, 0xF3, 0x0F, 0x2A, _r},  {xmm32, r_m64}, D_U},
 END_OPCODES()
 END_MNEMONIC()
 
@@ -620,43 +620,43 @@
 
 BEGIN_MNEMONIC(FADDP, MF_NONE, DU )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDE, 0xC1},       {FP0D}, DU },
-    {OpcodeInfo::all,   {0xDE, 0xC1},       {FP0S}, DU },
+    {OpcodeInfo::all, {0xDE, 0xC1},       {FP0D}, DU },
+    {OpcodeInfo::all, {0xDE, 0xC1},       {FP0S}, DU },
 END_OPCODES()
 END_MNEMONIC()
     
 BEGIN_MNEMONIC(FLDZ,  MF_NONE, U )                        
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xD9, 0xEE},   {FP0D}, D },
-    {OpcodeInfo::all,   {0xD9, 0xEE},   {FP0S}, D },
+    {OpcodeInfo::all, {0xD9, 0xEE},       {FP0D}, D },
+    {OpcodeInfo::all, {0xD9, 0xEE},       {FP0S}, D },
 END_OPCODES()
 END_MNEMONIC()
     
 BEGIN_MNEMONIC(FADD,  MF_NONE, U )                      
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDC, _0},     {FP0D, m64}, DU_U },
-    {OpcodeInfo::all,   {0xD8, _0},     {FP0S, m32}, DU_U },
+    {OpcodeInfo::all, {0xDC, _0},       {FP0D, m64}, DU_U },
+    {OpcodeInfo::all, {0xD8, _0},       {FP0S, m32}, DU_U },
 END_OPCODES()
 END_MNEMONIC()
     
 BEGIN_MNEMONIC(FSUBP, MF_NONE, DU )                       
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDE, 0xE9},   {FP0D}, DU },
-    {OpcodeInfo::all,   {0xDE, 0xE9},   {FP0S}, DU },
+    {OpcodeInfo::all, {0xDE, 0xE9},       {FP0D}, DU },
+    {OpcodeInfo::all, {0xDE, 0xE9},       {FP0S}, DU },
 END_OPCODES()
 END_MNEMONIC()
     
 BEGIN_MNEMONIC(FSUB,   MF_NONE, U )                     
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDC, _4},     {FP0D, m64}, DU_U },
-    {OpcodeInfo::all,   {0xD8, _4},     {FP0S, m32}, DU_U },
+    {OpcodeInfo::all, {0xDC, _4},       {FP0D, m64}, DU_U },
+    {OpcodeInfo::all, {0xD8, _4},       {FP0S, m32}, DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FISUB,   MF_NONE, U )                     
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDA, _4},       {FP0S, m32}, DU_U },
-//    {OpcodeInfo::all,   {0xDE, _4},       {FP0S, m16}, DU_U },
+    {OpcodeInfo::all, {0xDA, _4},       {FP0S, m32}, DU_U },
+//    {OpcodeInfo::all, {0xDE, _4},       {FP0S, m16}, DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -664,79 +664,79 @@
     
 BEGIN_MNEMONIC(FMUL,   MF_NONE, DU_U )                     
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xD8, _1},     {FP0S, m32}, DU_U },
-    {OpcodeInfo::all,   {0xDC, _1},     {FP0D, m64}, DU_U },
+    {OpcodeInfo::all, {0xD8, _1},       {FP0S, m32}, DU_U },
+    {OpcodeInfo::all, {0xDC, _1},       {FP0D, m64}, DU_U },
 END_OPCODES()
 END_MNEMONIC()
     
 BEGIN_MNEMONIC(FMULP, MF_NONE, DU )                       
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDE, 0xC9},   {FP0D}, DU },
-    {OpcodeInfo::all,   {0xDE, 0xC9},   {FP0S}, DU },
+    {OpcodeInfo::all, {0xDE, 0xC9},       {FP0D}, DU }, 
+    {OpcodeInfo::all, {0xDE, 0xC9},       {FP0S}, DU }, 
 END_OPCODES()
 END_MNEMONIC()
     
 BEGIN_MNEMONIC(FDIVP, MF_NONE, DU )                       
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDE, 0xF9},   {FP0D}, DU },
-    {OpcodeInfo::all,   {0xDE, 0xF9},   {FP0S}, DU },
+    {OpcodeInfo::all, {0xDE, 0xF9},       {FP0D}, DU },
+    {OpcodeInfo::all, {0xDE, 0xF9},       {FP0S}, DU },
 END_OPCODES()
 END_MNEMONIC()
     
 BEGIN_MNEMONIC(FDIV,   MF_NONE, U )                     
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDC, _6},     {FP0D, m64}, DU_U },
-    {OpcodeInfo::all,   {0xD8, _6},     {FP0S, m32}, DU_U },
+    {OpcodeInfo::all, {0xDC, _6},       {FP0D, m64}, DU_U },
+    {OpcodeInfo::all, {0xD8, _6},       {FP0S, m32}, DU_U },
 END_OPCODES()
 END_MNEMONIC()
     
 BEGIN_MNEMONIC(FUCOMPP, MF_NONE, U )                       
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDA, 0xE9},   {FP0D, FP1D}, DU_U },
-    {OpcodeInfo::all,   {0xDA, 0xE9},   {FP0S, FP1S}, DU_U },
+    {OpcodeInfo::all, {0xDA, 0xE9},       {FP0D, FP1D}, DU_U },
+    {OpcodeInfo::all, {0xDA, 0xE9},       {FP0S, FP1S}, DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FLDCW, MF_NONE, U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xD9, _5},     {m16},  U },
+    {OpcodeInfo::all, {0xD9, _5}, {m16},  U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FNSTCW, MF_NONE, D)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xD9, _7},     {m16},  D },
+    {OpcodeInfo::all, {0xD9, _7}, {m16},  D },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FSTSW, MF_NONE, D)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x9B, 0xDF, 0xE0}, {EAX},  D },
+    {OpcodeInfo::all, {0x9B, 0xDF, 0xE0}, {EAX},     D },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FNSTSW, MF_NONE, D)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDF, 0xE0},   {EAX},  D },
+    {OpcodeInfo::all, {0xDF, 0xE0}, {EAX},     D },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FCHS, MF_NONE, DU )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xD9, 0xE0},   {FP0D}, DU },
-    {OpcodeInfo::all,   {0xD9, 0xE0},   {FP0S}, DU },
+    {OpcodeInfo::all, {0xD9, 0xE0},       {FP0D}, DU },
+    {OpcodeInfo::all, {0xD9, 0xE0},       {FP0S}, DU },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FCLEX, MF_NONE, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x9B, 0xDB, 0xE2}, {}, N },
+    {OpcodeInfo::all, {0x9B, 0xDB, 0xE2}, {},   N },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FNCLEX, MF_NONE, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDB, 0xE2},       {}, N },
+    {OpcodeInfo::all, {0xDB, 0xE2},     {},     N },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -748,9 +748,9 @@
 
 BEGIN_MNEMONIC(FILD, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDB, _0}, {FP0S, m32},    D_U },
-    {OpcodeInfo::all,   {0xDF, _5}, {FP0D, m64},    D_U },
-    {OpcodeInfo::all,   {0xDB, _0}, {FP0S, m32},    D_U },
+    {OpcodeInfo::all, {0xDB, _0}, {FP0S, m32},    D_U },
+    {OpcodeInfo::all, {0xDF, _5}, {FP0D, m64},    D_U },
+    {OpcodeInfo::all, {0xDB, _0}, {FP0S, m32},    D_U },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -762,56 +762,56 @@
 
 BEGIN_MNEMONIC(FIST, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDB, _2}, {m32, FP0S},    D_U },
+    {OpcodeInfo::all, {0xDB, _2}, {m32, FP0S},    D_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FISTP, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDB, _3}, {m32, FP0S},    D_U },
-    {OpcodeInfo::all,   {0xDF, _7}, {m64, FP0D},    D_U },
+    {OpcodeInfo::all, {0xDB, _3}, {m32, FP0S},    D_U },
+    {OpcodeInfo::all, {0xDF, _7}, {m64, FP0D},    D_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FISTTP, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xDD, _1}, {m64, FP0D},    D_U },
-    {OpcodeInfo::all,   {0xDB, _1}, {m32, FP0S},    D_U },
+    {OpcodeInfo::all, {0xDD, _1}, {m64, FP0D},    D_U },
+    {OpcodeInfo::all, {0xDB, _1}, {m32, FP0S},    D_U },
 END_OPCODES()
 END_MNEMONIC()
     
 BEGIN_MNEMONIC(FRNDINT, MF_NONE, DU )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xD9, 0xFC}, {FP0S},    DU },
-    {OpcodeInfo::all,   {0xD9, 0xFC}, {FP0D},    DU },
+    {OpcodeInfo::all, {0xD9, 0xFC}, {FP0S},    DU },
+    {OpcodeInfo::all, {0xD9, 0xFC}, {FP0D},    DU },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FLD, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xD9, _0}, {FP0S, m32},    D_U },
-    {OpcodeInfo::all,   {0xDD, _0}, {FP0D, m64},    D_U },
+    {OpcodeInfo::all, {0xD9, _0}, {FP0S, m32},    D_U },
+    {OpcodeInfo::all, {0xDD, _0}, {FP0D, m64},    D_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FLDLG2, MF_NONE, U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xD9, 0xEC}, {FP0S},    D },
-    {OpcodeInfo::all,   {0xD9, 0xEC}, {FP0D},    D },
+    {OpcodeInfo::all, {0xD9, 0xEC}, {FP0S},    D },
+    {OpcodeInfo::all, {0xD9, 0xEC}, {FP0D},    D },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FLDLN2, MF_NONE, U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xD9, 0xED}, {FP0S},    D },
-    {OpcodeInfo::all,   {0xD9, 0xED}, {FP0D},    D }, 
+    {OpcodeInfo::all, {0xD9, 0xED}, {FP0S},    D },
+    {OpcodeInfo::all, {0xD9, 0xED}, {FP0D},    D }, 
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(FLD1, MF_NONE, U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xD9, 0xE8}, {FP0S},    D },
-    {OpcodeInfo::all,   {0xD9, 0xE8}, {FP0D},    D }, 
+    {OpcodeInfo::all, {0xD9, 0xE8}, {FP0S},    D },
+    {OpcodeInfo::all, {0xD9, 0xE8}, {FP0D},    D }, 
 END_OPCODES()
 END_MNEMONIC()
 
@@ -824,7 +824,7 @@
 
 BEGIN_MNEMONIC(FPREM1, MF_NONE, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xD9, 0xF5},       {},     N },
+    {OpcodeInfo::all, {0xD9, 0xF5},       {},     N },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -949,7 +949,7 @@
 #endif
     {OpcodeInfo::all,   {0xF7, _7},         {EDX, EAX, r_m32},  DU_DU_U },
     {OpcodeInfo::em64t, {REX_W, 0xF7, _7},  {RDX, RAX, r_m64},  DU_DU_U },
-END_OPCODES()
+    END_OPCODES()
 END_MNEMONIC()
 
 
@@ -965,53 +965,53 @@
     // revisit the hash implementation
     // {OpcodeInfo::em64t,   {REX_W, 0xF7, _5},        {RDX, RAX, r_m64},  D_DU_U },
     //
-    {OpcodeInfo::all,   {Size16, 0x0F, 0xAF, _r}, {r16,r_m16},        DU_U },
-    {OpcodeInfo::all,   {0x0F, 0xAF, _r},         {r32,r_m32},        DU_U },
-    {OpcodeInfo::em64t, {REX_W, 0x0F, 0xAF, _r},  {r64,r_m64},        DU_U },
-    {OpcodeInfo::all,   {Size16, 0x6B, _r, ib},   {r16,r_m16,imm8s},  D_DU_U },
-    {OpcodeInfo::all,   {0x6B, _r, ib},           {r32,r_m32,imm8s},  D_DU_U },
-    {OpcodeInfo::em64t, {REX_W, 0x6B, _r, ib},    {r64,r_m64,imm8s},  D_DU_U },
-    {OpcodeInfo::all,   {Size16, 0x6B, _r, ib},   {r16,imm8s},        DU_U },
-    {OpcodeInfo::all,   {0x6B, _r, ib},           {r32,imm8s},        DU_U },
-    {OpcodeInfo::em64t, {REX_W, 0x6B, _r, ib},    {r64,imm8s},        DU_U },
-    {OpcodeInfo::all,   {Size16, 0x69, _r, iw},   {r16,r_m16,imm16},  D_U_U },
-    {OpcodeInfo::all,   {0x69, _r, id},           {r32,r_m32,imm32},  D_U_U },
-    {OpcodeInfo::em64t, {REX_W, 0x69, _r, id},    {r64,r_m64,imm32s}, D_U_U },
+    {OpcodeInfo::all,     {Size16, 0x0F, 0xAF, _r}, {r16,r_m16},        DU_U },
+    {OpcodeInfo::all,     {0x0F, 0xAF, _r},         {r32,r_m32},        DU_U },
+    {OpcodeInfo::em64t,   {REX_W, 0x0F, 0xAF, _r},  {r64,r_m64},        DU_U },
+    {OpcodeInfo::all,     {Size16, 0x6B, _r, ib},   {r16,r_m16,imm8},   D_DU_U },
+    {OpcodeInfo::all,     {0x6B, _r, ib},           {r32,r_m32,imm8},   D_DU_U },
+    {OpcodeInfo::em64t,   {REX_W, 0x6B, _r, ib},    {r64,r_m64,imm8},   D_DU_U },
+    {OpcodeInfo::all,     {Size16, 0x6B, _r, ib},   {r16,imm8},         DU_U },
+    {OpcodeInfo::all,     {0x6B, _r, ib},           {r32,imm8},         DU_U },
+    {OpcodeInfo::em64t,   {REX_W, 0x6B, _r, ib},    {r64,imm8},         DU_U },
+    {OpcodeInfo::all,     {Size16, 0x69, _r, iw},   {r16,r_m16,imm16},  D_U_U },
+    {OpcodeInfo::all,     {0x69, _r, id},           {r32,r_m32,imm32},  D_U_U },
+    {OpcodeInfo::em64t,   {REX_W, 0x69, _r, id},    {r64,r_m64,imm32},  D_U_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(MUL, MF_AFFECTS_FLAGS, U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF6, _4},           {AX, AL, r_m8},     D_DU_U },
-    {OpcodeInfo::all,   {Size16, 0xF7, _4},   {DX, AX, r_m16},    D_DU_U },
-    {OpcodeInfo::all,   {0xF7, _4},           {EDX, EAX, r_m32},  D_DU_U },
-    {OpcodeInfo::em64t, {REX_W, 0xF7, _4},    {RDX, RAX, r_m64},  D_DU_U },
+    {OpcodeInfo::all,     {0xF6, _4},           {AX, AL, r_m8},     D_DU_U },
+    {OpcodeInfo::all,     {Size16, 0xF7, _4},   {DX, AX, r_m16},    D_DU_U },
+    {OpcodeInfo::all,     {0xF7, _4},           {EDX, EAX, r_m32},  D_DU_U },
+    {OpcodeInfo::em64t,   {REX_W, 0xF7, _4},    {RDX, RAX, r_m64},  D_DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(INC, MF_AFFECTS_FLAGS, DU )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xFE, _0},           {r_m8},         DU },
-    {OpcodeInfo::all,   {Size16, 0xFF, _0},   {r_m16},        DU },
-    {OpcodeInfo::all,   {0xFF, _0},           {r_m32},        DU },
-    {OpcodeInfo::em64t, {REX_W, 0xFF, _0},    {r_m64},        DU },
-    {OpcodeInfo::ia32,  {Size16, 0x40|rw},    {r16},          DU },
-    {OpcodeInfo::ia32,  {0x40|rd},            {r32},          DU },
+    {OpcodeInfo::all,     {0xFE, _0},           {r_m8},         DU },
+    {OpcodeInfo::all,     {Size16, 0xFF, _0},   {r_m16},        DU },
+    {OpcodeInfo::all,     {0xFF, _0},           {r_m32},        DU },
+    {OpcodeInfo::em64t,   {REX_W, 0xFF, _0},    {r_m64},        DU },
+    {OpcodeInfo::ia32,    {Size16, 0x40|rw},    {r16},          DU },
+    {OpcodeInfo::ia32,    {0x40|rd},            {r32},          DU },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(INT3, MF_NONE, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xCC},     {},     N },
+    {OpcodeInfo::all, {0xCC},     {},     N },
 END_OPCODES()
 END_MNEMONIC()
 
 #define DEFINE_Jcc_MNEMONIC( cc ) \
         BEGIN_MNEMONIC(J##cc, MF_USES_FLAGS|MF_CONDITIONAL, U ) \
 BEGIN_OPCODES() \
-    {OpcodeInfo::all,   {0x70 + ConditionMnemonic_##cc, cb },           { rel8 },       U }, \
-    {OpcodeInfo::ia32,  {Size16, 0x0F, 0x80 + ConditionMnemonic_##cc, cw},      { rel16 },      U }, \
-    {OpcodeInfo::all,   {0x0F, 0x80 + ConditionMnemonic_##cc, cd},      { rel32 },      U }, \
+    {OpcodeInfo::all,     {0x70 + ConditionMnemonic_##cc, cb },           { rel8 },       U }, \
+    {OpcodeInfo::ia32,    {Size16, 0x0F, 0x80 + ConditionMnemonic_##cc, cw},      { rel16 },      U }, \
+    {OpcodeInfo::all,     {0x0F, 0x80 + ConditionMnemonic_##cc, cd},      { rel32 },      U }, \
 END_OPCODES() \
 END_MNEMONIC()
 
@@ -1074,43 +1074,45 @@
 
 BEGIN_MNEMONIC(LOOP, MF_AFFECTS_FLAGS|MF_USES_FLAGS, DU_U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xE2, cb},     {ECX, rel8},    DU_U },
+    {OpcodeInfo::all,     {0xE2, cb},     {ECX, rel8},    DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(LOOPE, MF_AFFECTS_FLAGS|MF_USES_FLAGS, DU_U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xE1, cb},     {ECX, rel8},    DU_U },
+    {OpcodeInfo::all,     {0xE1, cb},     {ECX, rel8},    DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(LOOPNE, MF_AFFECTS_FLAGS|MF_USES_FLAGS, DU_U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xE0, cb},     {ECX, rel8},    DU_U },
+    {OpcodeInfo::all,     {0xE0, cb},     {ECX, rel8},    DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(MOV, MF_NONE, D_U)
 BEGIN_OPCODES()
     {OpcodeInfo::all,   {0x88, _r},         {r_m8,r8},      D_U },
+
     {OpcodeInfo::all,   {Size16, 0x89, _r}, {r_m16,r16},    D_U },
     {OpcodeInfo::all,   {0x89, _r},         {r_m32,r32},    D_U },
     {OpcodeInfo::em64t, {REX_W, 0x89, _r},  {r_m64,r64},    D_U },
-
     {OpcodeInfo::all,   {0x8A, _r},         {r8,r_m8},      D_U },
+
     {OpcodeInfo::all,   {Size16, 0x8B, _r}, {r16,r_m16},    D_U },
     {OpcodeInfo::all,   {0x8B, _r},         {r32,r_m32},    D_U },
     {OpcodeInfo::em64t, {REX_W, 0x8B, _r},  {r64,r_m64},    D_U },
 
     {OpcodeInfo::all,   {0xB0|rb},          {r8,imm8},      D_U },
+
     {OpcodeInfo::all,   {Size16, 0xB8|rw},  {r16,imm16},    D_U },
     {OpcodeInfo::all,   {0xB8|rd},          {r32,imm32},    D_U },
     {OpcodeInfo::em64t, {REX_W, 0xB8|rd},   {r64,imm64},    D_U },
-
     {OpcodeInfo::all,   {0xC6, _0},         {r_m8,imm8},    D_U },
+
     {OpcodeInfo::all,   {Size16, 0xC7, _0}, {r_m16,imm16},  D_U },
     {OpcodeInfo::all,   {0xC7, _0},         {r_m32,imm32},  D_U },
-    {OpcodeInfo::em64t, {REX_W, 0xC7, _0},  {r_m64,imm32s}, D_U },
+    {OpcodeInfo::em64t, {REX_W, 0xC7, _0},  {r_m64,imm32},  D_U },
 
     {OpcodeInfo::decoder,   {0xA0},         {AL,  moff8},  D_U },
     {OpcodeInfo::decoder,   {Size16, 0xA1}, {AX,  moff16},  D_U },
@@ -1128,7 +1130,7 @@
 
 BEGIN_MNEMONIC(XCHG, MF_NONE, DU_DU )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x87, _r},   {r_m32,r32},    DU_DU },
+    {OpcodeInfo::all,     {0x87, _r},   {r_m32,r32},    DU_DU },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1136,11 +1138,11 @@
 BEGIN_MNEMONIC(MOVQ, MF_NONE, D_U )
 BEGIN_OPCODES()
 #ifdef _HAVE_MMX_
-    {OpcodeInfo::all,   {0x0F, 0x6F, _r},   {mm64, mm_m64}, D_U },
-    {OpcodeInfo::all,   {0x0F, 0x7F, _r},   {mm_m64, mm64}, D_U },
+    {OpcodeInfo::all, {0x0F, 0x6F, _r},   {mm64, mm_m64}, D_U },
+    {OpcodeInfo::all, {0x0F, 0x7F, _r},   {mm_m64, mm64}, D_U },
 #endif
-    {OpcodeInfo::all,   {0xF3, 0x0F, 0x7E },  {xmm64, xmm_m64},       D_U },
-    {OpcodeInfo::all,   {0x66, 0x0F, 0xD6 },  {xmm_m64, xmm64},       D_U },
+    {OpcodeInfo::all, {0xF3, 0x0F, 0x7E },  {xmm64, xmm_m64},       D_U },
+    {OpcodeInfo::all, {0x66, 0x0F, 0xD6 },  {xmm_m64, xmm64},       D_U },
 //    {OpcodeInfo::em64t, {REX_W, 0x66, 0x0F, 0x6E, _r},  {xmm64, r_m64}, D_U },
 //    {OpcodeInfo::em64t, {REX_W, 0x66, 0x0F, 0x7E, _r},  {r_m64, xmm64}, D_U },
     {OpcodeInfo::em64t, {REX_W, 0x66, 0x0F, 0x6E, _r},  {xmm64, r64}, D_U },
@@ -1163,7 +1165,7 @@
 
 BEGIN_MNEMONIC(EMMS, MF_NONE, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x0F, 0x77},       {},             N },
+    {OpcodeInfo::all, {0x0F, 0x77},       {},             N },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1205,8 +1207,8 @@
 
 BEGIN_MNEMONIC(MOVAPD, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x66, 0x0F, 0x28, _r},   {xmm64, xmm_m64},   D_U },
-    {OpcodeInfo::all,   {0x66, 0x0F, 0x29, _r},   {xmm_m64, xmm64},   D_U },
+    {OpcodeInfo::all, {0x66, 0x0F, 0x28, _r},   {xmm64, xmm_m64},   D_U },
+    {OpcodeInfo::all, {0x66, 0x0F, 0x29, _r},   {xmm_m64, xmm64},   D_U },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1227,28 +1229,28 @@
 
 BEGIN_MNEMONIC(MOVSX, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,       {Size16, 0x0F, 0xBE, _r}, {r16, r_m8s},     D_U },
-    {OpcodeInfo::all,       {0x0F, 0xBE, _r},         {r32, r_m8s},     D_U },
-    {OpcodeInfo::em64t,     {REX_W, 0x0F, 0xBE, _r},  {r64, r_m8s},     D_U },
+    {OpcodeInfo::all,     {Size16, 0x0F, 0xBE, _r}, {r16, r_m8},    D_U },
+    {OpcodeInfo::all,     {0x0F, 0xBE, _r},         {r32, r_m8},    D_U },
+    {OpcodeInfo::em64t,   {REX_W, 0x0F, 0xBE, _r},  {r64, r_m8},    D_U },
     
-    {OpcodeInfo::all,       {0x0F, 0xBF, _r},         {r32, r_m16s},    D_U },
-    {OpcodeInfo::em64t,     {REX_W, 0x0F, 0xBF, _r},  {r64, r_m16s},    D_U },
+    {OpcodeInfo::all,     {0x0F, 0xBF, _r},         {r32, r_m16},   D_U },
+    {OpcodeInfo::em64t,   {REX_W, 0x0F, 0xBF, _r},  {r64, r_m16},   D_U },
     
-    {OpcodeInfo::em64t,     {REX_W, 0x63, _r},        {r64, r_m32s},    D_U },
+    {OpcodeInfo::em64t,   {REX_W, 0x63, _r},        {r64, r_m32},   D_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(MOVZX, MF_NONE, D_U )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,       {Size16, 0x0F, 0xB6, _r}, {r16, r_m8u},     D_U },
-    {OpcodeInfo::all,       {0x0F, 0xB6, _r},         {r32, r_m8u},     D_U },
-    {OpcodeInfo::em64t,     {REX_W, 0x0F, 0xB6, _r},  {r64, r_m8u},     D_U },
+    {OpcodeInfo::all,     {Size16, 0x0F, 0xB6, _r}, {r16, r_m8},    D_U },
+    {OpcodeInfo::all,     {0x0F, 0xB6, _r},         {r32, r_m8},    D_U },
+    {OpcodeInfo::em64t,   {REX_W, 0x0F, 0xB6, _r},  {r64, r_m8},    D_U },
 
-    {OpcodeInfo::all,       {0x0F, 0xB7, _r},         {r32, r_m16u},    D_U },
-    {OpcodeInfo::em64t,     {REX_W, 0x0F, 0xB7, _r},  {r64, r_m16u},    D_U },
+    {OpcodeInfo::all,     {0x0F, 0xB7, _r},         {r32, r_m16},   D_U },
+    {OpcodeInfo::em64t,   {REX_W, 0x0F, 0xB7, _r},  {r64, r_m16},   D_U },
     //workaround to get r/rm32->r64 ZX mov functionality:
     //simple 32bit reg copying zeros high bits in 64bit reg
-    {OpcodeInfo::em64t,     {0x8B, _r},               {r64, r_m32u},    D_U },
+    {OpcodeInfo::em64t,   {0x8B, _r},  {r64, r_m32},   D_U },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1260,7 +1262,7 @@
 
 BEGIN_MNEMONIC(MULSS, MF_NONE, DU_U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF3, 0x0F, 0x59, _r}, {xmm32, xmm_m32}, DU_U },
+    {OpcodeInfo::all,     {0xF3, 0x0F, 0x59, _r}, {xmm32, xmm_m32}, DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1276,16 +1278,16 @@
 
 BEGIN_MNEMONIC(NOP, MF_NONE, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x90}, {},     N },
+    {OpcodeInfo::all,     {0x90}, {},     N },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(NOT, MF_AFFECTS_FLAGS, DU )
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF6, _2},           {r_m8},         DU },
-    {OpcodeInfo::all,   {Size16, 0xF7, _2},   {r_m16},        DU },
-    {OpcodeInfo::all,   {0xF7, _2},           {r_m32},        DU },
-    {OpcodeInfo::em64t, {REX_W, 0xF7, _2},    {r_m64},        DU },
+    {OpcodeInfo::all,     {0xF6, _2},           {r_m8},         DU },
+    {OpcodeInfo::all,     {Size16, 0xF7, _2},   {r_m16},        DU },
+    {OpcodeInfo::all,     {0xF7, _2},           {r_m32},        DU },
+    {OpcodeInfo::em64t,   {REX_W, 0xF7, _2},    {r_m64},        DU },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1309,7 +1311,7 @@
 
 BEGIN_MNEMONIC(PREFETCH, MF_NONE, U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x0F, 0x18, _0},   {m8},         U },
+{OpcodeInfo::all,   {0x0F, 0x18, _0},   {m8},         U },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1332,22 +1334,22 @@
 
 BEGIN_MNEMONIC(PUSHFD, MF_USES_FLAGS, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x9C},             {},        N },
+    {OpcodeInfo::all,     {0x9C},             {},        N },
 END_OPCODES()
 END_MNEMONIC()
 
 
 BEGIN_MNEMONIC(RET, MF_NONE, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xC3},       {},         N },
-    {OpcodeInfo::all,   {0xC2, iw},   {imm16},    U },
+    {OpcodeInfo::all, {0xC3},       {},         N },
+    {OpcodeInfo::all, {0xC2, iw},   {imm16},    U },
 END_OPCODES()
 END_MNEMONIC()
 
 #define DEFINE_SETcc_MNEMONIC( cc ) \
         BEGIN_MNEMONIC(SET##cc, MF_USES_FLAGS|MF_CONDITIONAL, DU) \
 BEGIN_OPCODES() \
-    {OpcodeInfo::all,   {0x0F,     0x90 + ConditionMnemonic_##cc}, {r_m8},  DU }, \
+    {OpcodeInfo::all, {0x0F, 0x90 + ConditionMnemonic_##cc}, {r_m8},  DU }, \
 END_OPCODES() \
 END_MNEMONIC()
 
@@ -1376,22 +1378,22 @@
 BEGIN_OPCODES()\
     /* D0 & D1 opcodes are added w/o 2nd operand (1) because */\
     /* they are used for decoding only so only instruction length is needed */\
-    {OpcodeInfo::decoder,   {0xD0, slash_num},            {r_m8/*,const_1*/},   DU },\
-    {OpcodeInfo::all,       {0xD2, slash_num},              {r_m8,  CL},        DU_U },\
-    {OpcodeInfo::all,       {0xC0, slash_num, ib},          {r_m8,  imm8},      DU_U },\
+    {OpcodeInfo::decoder, {0xD0, slash_num},            {r_m8/*,const_1*/},   DU },\
+    {OpcodeInfo::all,   {0xD2, slash_num},              {r_m8,  CL},        DU_U },\
+    {OpcodeInfo::all,   {0xC0, slash_num, ib},          {r_m8,  imm8},      DU_U },\
 \
-    {OpcodeInfo::decoder,   {Size16, 0xD1, slash_num},    {r_m16/*,const_1*/},  DU },\
-    {OpcodeInfo::all,       {Size16, 0xD3, slash_num},      {r_m16, CL},        DU_U },\
-    {OpcodeInfo::all,       {Size16, 0xC1, slash_num, ib},  {r_m16, imm8 },     DU_U },\
+    {OpcodeInfo::decoder, {Size16, 0xD1, slash_num},    {r_m16/*,const_1*/},  DU },\
+    {OpcodeInfo::all,   {Size16, 0xD3, slash_num},      {r_m16, CL},        DU_U },\
+    {OpcodeInfo::all,   {Size16, 0xC1, slash_num, ib},  {r_m16, imm8 },     DU_U },\
 \
     {OpcodeInfo::decoder,   {0xD1, slash_num},              {r_m32/*,const_1*/}, DU },\
     {OpcodeInfo::decoder64, {REX_W, 0xD1, slash_num},       {r_m64/*,const_1*/}, DU },\
 \
-    {OpcodeInfo::all,       {0xD3, slash_num},              {r_m32, CL},        DU_U },\
-    {OpcodeInfo::em64t,     {REX_W, 0xD3, slash_num},       {r_m64, CL},        DU_U },\
+    {OpcodeInfo::all,   {0xD3, slash_num},              {r_m32, CL},        DU_U },\
+    {OpcodeInfo::em64t, {REX_W, 0xD3, slash_num},       {r_m64, CL},        DU_U },\
 \
-    {OpcodeInfo::all,       {0xC1, slash_num, ib},          {r_m32, imm8},      DU_U },\
-    {OpcodeInfo::em64t,     {REX_W, 0xC1, slash_num, ib},   {r_m64, imm8},      DU_U },\
+    {OpcodeInfo::all,   {0xC1, slash_num, ib},          {r_m32, imm8},      DU_U },\
+    {OpcodeInfo::em64t, {REX_W, 0xC1, slash_num, ib},   {r_m64, imm8},      DU_U },\
 END_OPCODES()\
 END_MNEMONIC()
 
@@ -1409,50 +1411,50 @@
 
 BEGIN_MNEMONIC(SHLD, MF_AFFECTS_FLAGS, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x0F, 0xA5},   {r_m32, r32, CL}, DU_DU_U },
-    {OpcodeInfo::all,   {0x0F, 0xA4},   {r_m32, r32, imm8}, DU_DU_U },
+    {OpcodeInfo::all,     {0x0F, 0xA5},   {r_m32, r32, ECX}, DU_DU_U },
+    {OpcodeInfo::all,     {0x0F, 0xA4},   {r_m32, r32, imm8}, DU_DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(SHRD, MF_AFFECTS_FLAGS, N)
 // TODO: the def/use info is wrong
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x0F, 0xAD},   {r_m32, r32, CL}, DU_DU_U },
+    {OpcodeInfo::all,     {0x0F, 0xAD},   {r_m32, r32, ECX}, DU_DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
 
 BEGIN_MNEMONIC(SUBSD, MF_NONE, DU_U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF2, 0x0F, 0x5C, _r}, {xmm64, xmm_m64}, DU_U },
+    {OpcodeInfo::all,     {0xF2, 0x0F, 0x5C, _r}, {xmm64, xmm_m64}, DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(SUBSS, MF_NONE, DU_U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xF3, 0x0F, 0x5C, _r}, {xmm32, xmm_m32}, DU_U },
+    {OpcodeInfo::all,     {0xF3, 0x0F, 0x5C, _r}, {xmm32, xmm_m32}, DU_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(TEST, MF_AFFECTS_FLAGS, U_U)
 BEGIN_OPCODES()
 
-    {OpcodeInfo::decoder,   {0xA8, ib},             { AL, imm8},    U_U },
-    {OpcodeInfo::decoder,   {0xA9, iw},             { AX, imm16},   U_U },
-    {OpcodeInfo::decoder,   {0xA9, id},             { EAX, imm32},  U_U },
-    {OpcodeInfo::decoder64, {REX_W, 0xA9, id},      { RAX, imm32s}, U_U },
-
-    {OpcodeInfo::all,       {0xF6, _0, ib},         {r_m8,imm8},    U_U },
-
-    {OpcodeInfo::all,       {Size16, 0xF7, _0, iw}, {r_m16,imm16},  U_U },
-    {OpcodeInfo::all,       {0xF7, _0, id},         {r_m32,imm32},  U_U },
-    {OpcodeInfo::em64t,     {REX_W, 0xF7, _0, id},  {r_m64,imm32s}, U_U },
-
-    {OpcodeInfo::all,       {0x84, _r},             {r_m8,r8},      U_U },
-
-    {OpcodeInfo::all,       {Size16, 0x85, _r},     {r_m16,r16},    U_U },
-    {OpcodeInfo::all,       {0x85, _r},             {r_m32,r32},    U_U },
-    {OpcodeInfo::em64t,     {REX_W, 0x85, _r},      {r_m64,r64},    U_U },
+    {OpcodeInfo::decoder,   {0xA8, ib},               { AL, imm8},    U_U },
+    {OpcodeInfo::decoder,   {0xA9, iw},               { AX, imm16},   U_U },
+    {OpcodeInfo::decoder,   {0xA9, id},               { EAX, imm32},  U_U },
+    {OpcodeInfo::decoder64, {REX_W, 0xA9, id},        { RAX, imm32},  U_U },
+
+    {OpcodeInfo::all,   {0xF6, _0, ib},         {r_m8,imm8},   U_U },
+
+    {OpcodeInfo::all,   {Size16, 0xF7, _0, iw}, {r_m16,imm16}, U_U },
+    {OpcodeInfo::all,   {0xF7, _0, id},         {r_m32,imm32}, U_U },
+    {OpcodeInfo::em64t, {REX_W, 0xF7, _0, id},  {r_m64,imm32}, U_U },
+
+    {OpcodeInfo::all,   {0x84, _r},             {r_m8,r8},     U_U },
+
+    {OpcodeInfo::all,   {Size16, 0x85, _r},     {r_m16,r16},   U_U },
+    {OpcodeInfo::all,   {0x85, _r},             {r_m32,r32},   U_U },
+    {OpcodeInfo::em64t, {REX_W, 0x85, _r},      {r_m64,r64},   U_U },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1465,19 +1467,19 @@
 
 BEGIN_MNEMONIC(UCOMISS, MF_AFFECTS_FLAGS, U_U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x0F, 0x2E, _r},       {xmm32, xmm_m32}, U_U },
+    {OpcodeInfo::all,     {0x0F, 0x2E, _r},       {xmm32, xmm_m32}, U_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(COMISD, MF_AFFECTS_FLAGS, U_U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x66, 0x0F, 0x2F, _r}, {xmm64, xmm_m64}, U_U },
+    {OpcodeInfo::all,     {0x66, 0x0F, 0x2F, _r}, {xmm64, xmm_m64}, U_U },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(COMISS, MF_AFFECTS_FLAGS, U_U)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x0F, 0x2F, _r},       {xmm32, xmm_m32}, U_U },
+    {OpcodeInfo::all,     {0x0F, 0x2F, _r},       {xmm32, xmm_m32}, U_U },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1528,13 +1530,13 @@
 //
 BEGIN_MNEMONIC(STD, MF_AFFECTS_FLAGS, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xFD},         {},     N },
+    {OpcodeInfo::all,     {0xFD},         {},     N },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(CLD, MF_AFFECTS_FLAGS, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xFC},         {},     N },
+    {OpcodeInfo::all,     {0xFC},         {},     N },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1543,7 +1545,7 @@
 // but as long, as Jitrino's CG does not use the mnemonic, leaving it
 // in its natural form
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0xAF},         {},     N },
+    {OpcodeInfo::all,     {0xAF},         {},     N },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1615,7 +1617,7 @@
 
 BEGIN_MNEMONIC(WAIT, MF_AFFECTS_FLAGS, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::all,   {0x9B},         {},       N },
+    {OpcodeInfo::all,     {0x9B},         {},       N },
 END_OPCODES()
 END_MNEMONIC()
 
@@ -1629,13 +1631,13 @@
 //
 BEGIN_MNEMONIC(LEAVE, MF_NONE, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::decoder,   {0xC9},         {},       N },
+    {OpcodeInfo::decoder,     {0xC9},         {},       N },
 END_OPCODES()
 END_MNEMONIC()
 
 BEGIN_MNEMONIC(ENTER, MF_NONE, N)
 BEGIN_OPCODES()
-    {OpcodeInfo::decoder,   {0xC8, iw, ib},           {imm16, imm8},  N },
+    {OpcodeInfo::decoder,     {0xC8, iw, ib},           {imm16, imm8},  N },
 END_OPCODES()
 END_MNEMONIC()
 

Modified: harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/encoder.h
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/encoder.h?rev=706374&r1=706373&r2=706374&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/encoder.h (original)
+++ harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/encoder.h Mon Oct 20 12:18:01 2008
@@ -193,7 +193,7 @@
 class Opnd {
 
 protected:
-    enum Tag { SignedImm, UnsignedImm, Reg, Mem, FP, XMM };
+    enum Tag { Imm, Reg, Mem, FP, XMM };
 
     const Tag  tag;
 
@@ -229,28 +229,18 @@
     Opnd_Size           size;
 
 public:
-    Imm_Opnd(I_32 val, bool isSigned = true):
-        Opnd(isSigned ? SignedImm : UnsignedImm), value(val), size(size_32) {
-        if (isSigned) {
-            if (CHAR_MIN <= val && val <= CHAR_MAX) {
-                size = size_8;
-            } else if (SHRT_MIN <= val && val <= SHRT_MAX) {
-                size = size_16;
-            }
-        } else {
-            assert(val >= 0);
-            if (val <= UCHAR_MAX) {
-                size = size_8;
-            } else if (val <= USHRT_MAX) {
-                size = size_16;
-            }
+    Imm_Opnd(I_32 val): Opnd(Imm), value(val), size(size_32) {
+        if (CHAR_MIN <= val && val <= CHAR_MAX) {
+            size = size_8;
+        }
+        else if (SHRT_MIN <= val && val <= SHRT_MAX) {
+            size = size_16;
         }
     }
-    Imm_Opnd(const Imm_Opnd& that): Opnd(that.tag), value(that.value), size(that.size) {};
+    Imm_Opnd(const Imm_Opnd& that): Opnd(Imm), value(that.value), size(that.size) {};
 
 #ifdef _EM64T_
-    Imm_Opnd(Opnd_Size sz, int64 val, bool isSigned = true):
-        Opnd(isSigned ? SignedImm : UnsignedImm), value(val), size(sz) {
+    Imm_Opnd(Opnd_Size sz, int64 val): Opnd(Imm), value(val), size(sz) {
 #ifndef NDEBUG
         switch (size) {
         case size_8:
@@ -275,8 +265,7 @@
 
 #else
 
-    Imm_Opnd(Opnd_Size sz, I_32 val, int isSigned = true):
-        Opnd(isSigned ? SignedImm : UnsignedImm), value(val), size(sz) {
+    Imm_Opnd(Opnd_Size sz, I_32 val): Opnd(Imm), value(val), size(sz) {
 #ifndef NDEBUG
         switch (size) {
         case size_8:
@@ -298,14 +287,13 @@
     I_32 get_value() const { return value; }
 
 #endif
-    Opnd_Size get_size() const { return size; }
-    bool      is_signed() const { return tag == SignedImm; }
+    Opnd_Size get_size(void) const { return size; }
 };
 
 class RM_Opnd: public Opnd {
 
 public:
-    bool is_reg() const { return tag != SignedImm && tag != UnsignedImm && tag != Mem; }
+    bool is_reg() const { return tag != Imm && tag != Mem; }
 
 protected:
     RM_Opnd(Tag t): Opnd(t) {}

Modified: harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/encoder.inl
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/encoder.inl?rev=706374&r1=706373&r2=706374&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/encoder.inl (original)
+++ harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/encoder.inl Mon Oct 20 12:18:01 2008
@@ -60,7 +60,7 @@
     return (INT_MIN <= val) && (val <= INT_MAX);
 }
 
-inline static void add_r(EncoderBase::Operands & args, const R_Opnd & r, Opnd_Size sz, OpndExt ext = OpndExt_None) {
+inline static void add_r(EncoderBase::Operands & args, const R_Opnd & r, Opnd_Size sz) {
     RegName reg = map_reg(r.reg_no());
     if (sz != n_size) {
         OpndSize size = map_size(sz);
@@ -68,18 +68,18 @@
             reg = getAliasReg(reg, size);
         }
     }
-    args.add(EncoderBase::Operand(reg, ext));
+    args.add(EncoderBase::Operand(reg));
 }
 
-inline static void add_m(EncoderBase::Operands & args, const M_Opnd & m, Opnd_Size sz, OpndExt ext = OpndExt_None) {
+inline static void add_m(EncoderBase::Operands & args, const M_Opnd & m, Opnd_Size sz) {
         assert(n_size != sz);
         args.add(EncoderBase::Operand(map_size(sz),
             map_reg(m.base().reg_no()), map_reg(m.index().reg_no()),
-            (unsigned)m.scale().get_value(), (int)m.disp().get_value(), ext));
+            (unsigned)m.scale().get_value(), (int)m.disp().get_value()));
 }
 
-inline static void add_rm(EncoderBase::Operands & args, const RM_Opnd & rm, Opnd_Size sz, OpndExt ext = OpndExt_None) {
-    rm.is_reg() ? add_r(args, (R_Opnd &)rm, sz, ext) : add_m(args, (M_Opnd &)rm, sz, ext);
+inline static void add_rm(EncoderBase::Operands & args, const RM_Opnd & rm, Opnd_Size sz) {
+    rm.is_reg() ? add_r(args, (R_Opnd &)rm, sz) : add_m(args, (M_Opnd &)rm, sz);
 }
 
 inline static void add_xmm(EncoderBase::Operands & args, const XMM_Opnd & xmm, bool dbl) {
@@ -98,8 +98,7 @@
 
 inline static void add_imm(EncoderBase::Operands & args, const Imm_Opnd & imm) {
     assert(n_size != imm.get_size());
-    args.add(EncoderBase::Operand(map_size(imm.get_size()), imm.get_value(),
-        imm.is_signed() ? OpndExt_Signed : OpndExt_Zero));
+    args.add(EncoderBase::Operand(map_size(imm.get_size()), imm.get_value()));
 }
 
 ENCODER_DECLARE_EXPORT char * prefix(char * stream, InstrPrefix p) {
@@ -210,7 +209,7 @@
     EncoderBase::Operands args;
     add_rm(args, rm, sz);
     assert(imm.get_size() <= sz);
-    add_imm(args, imm);
+    args.add(EncoderBase::Operand(map_size(size_32), imm.get_value()));
     return (char*)EncoderBase::encode(stream, Mnemonic_TEST, args);
 }
 
@@ -355,7 +354,7 @@
 ENCODER_DECLARE_EXPORT char * movsx(char * stream, const R_Opnd & r, const RM_Opnd & rm, Opnd_Size sz) {
     EncoderBase::Operands args;
     add_r(args, r, n_size);
-    add_rm(args, rm, sz, OpndExt_Signed);
+    add_rm(args, rm, sz);
     return (char*)EncoderBase::encode(stream, Mnemonic_MOVSX, args);
 }
 
@@ -365,7 +364,7 @@
     // movzx r64, r/m32 is not available on em64t
     // mov r32, r/m32 should zero out upper bytes
     assert(sz <= size_16);
-    add_rm(args, rm, sz, OpndExt_Zero);
+    add_rm(args, rm, sz);
     return (char*)EncoderBase::encode(stream, Mnemonic_MOVZX, args);
 }
 
@@ -737,7 +736,7 @@
 ENCODER_DECLARE_EXPORT char * ret(char * stream, unsigned short pop)
 {
     // TheManual says it can only be imm16
-    EncoderBase::Operands args(EncoderBase::Operand(OpndSize_16, pop, OpndExt_Zero));
+    EncoderBase::Operands args(EncoderBase::Operand(OpndSize_16, pop));
     return (char*)EncoderBase::encode(stream, Mnemonic_RET, args);
 }
 

Modified: harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/em64t/lil_code_generator_em64t.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/em64t/lil_code_generator_em64t.cpp?rev=706374&r1=706373&r2=706374&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/em64t/lil_code_generator_em64t.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/em64t/lil_code_generator_em64t.cpp Mon Oct 20 12:18:01 2008
@@ -635,8 +635,7 @@
     }
 
     void shift_op_rm_imm(const LcgEM64TLoc * dest, const LcgEM64TLoc * src, I_32 imm_val) {
-        assert(fit8(imm_val));
-        const Imm_Opnd & imm = get_imm_opnd(imm_val, size_8);
+        const Imm_Opnd & imm = get_imm_opnd(imm_val);
         if (src->kind == LLK_Gr) {
         if (dest->kind == LLK_Gr) {
             buf = mov(buf, get_r_opnd(dest), get_r_opnd(src), size_64);

Modified: harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/em64t/m2n_em64t.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/em64t/m2n_em64t.cpp?rev=706374&r1=706373&r2=706374&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/em64t/m2n_em64t.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/em64t/m2n_em64t.cpp Mon Oct 20 12:18:01 2008
@@ -301,12 +301,12 @@
         Imm_Opnd(size_32, 0), size_64);
     // store current_frame_type
     bytes_to_m2n_top -= LcgEM64TContext::GR_SIZE;
-    assert(fit32(current_frame_type)); //FIXME31
+    assert(fit32(current_frame_type));
     buf = mov(buf, M_Base_Opnd(rsp_reg, bytes_to_m2n_top),
         Imm_Opnd(size_32, current_frame_type), size_64);
     // store a method associated with the current m2n frame
     bytes_to_m2n_top -= LcgEM64TContext::GR_SIZE;
-    if (fit32((int64)method)) { //FIXME31
+    if (fit32((int64)method)) {
         buf = mov(buf, M_Base_Opnd(rsp_reg, bytes_to_m2n_top),
             Imm_Opnd(size_32, (int64)method), size_64);
     } else {
@@ -316,7 +316,7 @@
     // store local object handles
     bytes_to_m2n_top -= LcgEM64TContext::GR_SIZE;
     buf = mov(buf, M_Base_Opnd(rsp_reg, bytes_to_m2n_top),
-        Imm_Opnd(size_32, (int64)0), size_64);
+        Imm_Opnd(size_64, (int64)0), size_64);
 
     // move pointer to the current VM_Thread structure to rax
     buf = m2n_gen_ts_to_register(buf, &rax_opnd,

Modified: harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/lil_code_generator_ia32.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/lil_code_generator_ia32.cpp?rev=706374&r1=706373&r2=706374&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/lil_code_generator_ia32.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/lil_code_generator_ia32.cpp Mon Oct 20 12:18:01 2008
@@ -900,7 +900,7 @@
     case LOLT_Immed: {
         R_Opnd* tmp = get_temp_register(c, *temp_reg);
         ++*temp_reg;
-        *buf = mov(*buf, *tmp, Imm_Opnd(size_32, loc->u.v));
+        *buf = mov(*buf, *tmp, Imm_Opnd(loc->u.v));
         return tmp;}
     default: DIE(("Unknown type")); for(;;);
     }
@@ -922,9 +922,9 @@
         }
         break;}
     case LOLT_Immed: {
-        *buf = mov(*buf, *reg1, Imm_Opnd(size_32, loc->u.v));
+        *buf = mov(*buf, *reg1, Imm_Opnd(loc->u.v));
         if (two) {
-            *buf = mov(*buf, *reg2, Imm_Opnd(size_32,0));
+            *buf = mov(*buf, *reg2, Imm_Opnd(0));
         }
         break;}
     case LOLT_Tofs:{
@@ -1053,9 +1053,9 @@
             case LO_Mov:
                 // Treat immed->stack specially, the others are done by the movs o1->r->dst
                 if (ii->loc1.t==LOLT_Stack && ii->loc2.t==LOLT_Immed) {
-                    *buf = mov(*buf, M_Base_Opnd(esp_reg, ii->loc1.u.v), Imm_Opnd(size_32,ii->loc2.u.v));
+                    *buf = mov(*buf, M_Base_Opnd(esp_reg, ii->loc1.u.v), Imm_Opnd(ii->loc2.u.v));
                     if (type_in_two_regs(ii->t)) {
-                        *buf = mov(*buf, M_Base_Opnd(esp_reg, ii->loc1.u.v+4), Imm_Opnd(size_32, 0));
+                        *buf = mov(*buf, M_Base_Opnd(esp_reg, ii->loc1.u.v+4), Imm_Opnd(0));
                     }
                 }
                 break;
@@ -1197,7 +1197,7 @@
     {
         *buf = addr_emit_moves(*buf, &ii->u.address);
         if (ii->loc3.t==LOLT_Immed) {
-            Imm_Opnd imm(type_to_opnd_size(t),ii->loc3.u.v);
+            Imm_Opnd imm(ii->loc3.u.v);
             *buf = mov(*buf, *(ii->u.address.addr), imm, type_to_opnd_size(t));
         } else {
             R_Opnd* r = move_location_to_a_register(buf, &ctxt, &ii->loc3, &ii->temp_register);
@@ -1219,7 +1219,7 @@
         move_location_to_register(buf, &eax_opnd, NULL, &ii->loc3, t);
         *buf = prefix(*buf, lock_prefix);
         *buf = cmpxchg(*buf, *(ii->u.address.addr), *r, type_to_opnd_size(t));       
-        *buf = branch32(*buf, Condition_NZ, Imm_Opnd(size_32,-4));
+        *buf = branch32(*buf, Condition_NZ, Imm_Opnd(-4));
         la_tab.add_patch_to_label(l, *buf-4, LPT_Rel32);
     }
 

Modified: harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/m2n_ia32.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/m2n_ia32.cpp?rev=706374&r1=706373&r2=706374&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/m2n_ia32.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/m2n_ia32.cpp Mon Oct 20 12:18:01 2008
@@ -204,7 +204,7 @@
     buf = push(buf, Imm_Opnd(current_frame_type));
     
     int last_m2n_frame_offset = (int)&((VM_thread*)0)->last_m2n_frame;
-    Imm_Opnd imm1(size_32,last_m2n_frame_offset);
+    Imm_Opnd imm1(last_m2n_frame_offset);
     buf = alu(buf, add_opc,  eax_opnd,  imm1);
 
     Imm_Opnd imm2((unsigned)method);

Modified: harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/stack_iterator_ia32.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/stack_iterator_ia32.cpp?rev=706374&r1=706373&r2=706374&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/stack_iterator_ia32.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/vmcore/src/lil/ia32/stack_iterator_ia32.cpp Mon Oct 20 12:18:01 2008
@@ -180,8 +180,8 @@
     char* patch_offset = ((char *)ss) - 1; // Store location for jump patch
     *ss++ = (char)0x9C; // PUSHFD
     M_Base_Opnd m4(esp_reg, 0);
-    ss = alu(ss, and_opc, m4, Imm_Opnd(size_32,FLG_CLEAR_MASK));
-    ss = alu(ss, and_opc, ecx_opnd, Imm_Opnd(size_32,FLG_SET_MASK));
+    ss = alu(ss, and_opc, m4, Imm_Opnd(FLG_CLEAR_MASK));
+    ss = alu(ss, and_opc, ecx_opnd, Imm_Opnd(FLG_SET_MASK));
     ss = alu(ss, or_opc, m4, ecx_opnd);
     *ss++ = (char)0x9D; // POPFD
     // Patch conditional jump

Modified: harmony/enhanced/drlvm/trunk/vm/vmcore/src/thread/helpers/thread_helpers_ia32.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/vmcore/src/thread/helpers/thread_helpers_ia32.cpp?rev=706374&r1=706373&r2=706374&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/vmcore/src/thread/helpers/thread_helpers_ia32.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/vmcore/src/thread/helpers/thread_helpers_ia32.cpp Mon Oct 20 12:18:01 2008
@@ -124,7 +124,7 @@
 
 #ifdef LOCK_RESERVATION
 	ss = mov(ss, eax_opnd, M_Base_Opnd(ecx_reg, 1), size_8);            //  mov al, byte[ecx+1]
-    ss = test(ss,  eax_opnd,  Imm_Opnd(size_8, 0x4, false), size_8);    //  test al,0x4
+    ss = test(ss,  eax_opnd,  Imm_Opnd(size_8, 0x4), size_8);           //  test al,0x4
     ss = branch8(ss, Condition_NZ,  Imm_Opnd(size_8, 0));               //  jnz finish
     char *finish = ((char *)ss) - 1;
 

Modified: harmony/enhanced/drlvm/trunk/vm/vmcore/src/util/em64t/base/compile_em64t.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/vmcore/src/util/em64t/base/compile_em64t.cpp?rev=706374&r1=706373&r2=706374&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/vmcore/src/util/em64t/base/compile_em64t.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/vmcore/src/util/em64t/base/compile_em64t.cpp Mon Oct 20 12:18:01 2008
@@ -160,7 +160,7 @@
         ss = alu(ss, cmp_opc, input_param1, r11_opnd, size_64);
         ss = branch8(ss, Condition_NE, Imm_Opnd(size_8, 0));  // not null, branch around the mov 0
         char *backpatch_address__not_managed_null = ((char *)ss) - 1;
-        ss = mov(ss, input_param1, Imm_Opnd(size_32, 0));
+        ss = mov(ss, input_param1, Imm_Opnd(0));
         POINTER_SIZE_SINT offset = (POINTER_SIZE_SINT)ss - (POINTER_SIZE_SINT)backpatch_address__not_managed_null - 1;
         *backpatch_address__not_managed_null = (char)offset;
     REFS_RUNTIME_SWITCH_ENDIF
@@ -209,7 +209,7 @@
     assert(stack_size % 16 != 0);
 
     // set up stack frame
-	stub = alu(stub, sub_opc, rsp_opnd, Imm_Opnd(size_32, stack_size));
+    stub = alu(stub, sub_opc, rsp_opnd, Imm_Opnd(stack_size));
 
     // TODO: think over saving xmm registers conditionally
 #ifndef _WIN64
@@ -285,7 +285,7 @@
 #endif
 
     // adjust stack pointer
-    stub = alu(stub, add_opc, rsp_opnd, Imm_Opnd(size_32, stack_size));
+    stub = alu(stub, add_opc, rsp_opnd, Imm_Opnd(stack_size));
     // transfer control to the compiled code
     stub = jump(stub, rax_opnd);
     



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