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From "Ilya Berezhniuk (JIRA)" <j...@apache.org>
Subject [jira] Created: (HARMONY-5321) [drlvm][NCAI][encoder] JVMTI disassembler does not understand CMC opcode and D0/D1 shift opcodes
Date Mon, 17 Dec 2007 14:47:43 GMT
[drlvm][NCAI][encoder] JVMTI disassembler does not understand CMC opcode and D0/D1 shift opcodes
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                 Key: HARMONY-5321
                 URL: https://issues.apache.org/jira/browse/HARMONY-5321
             Project: Harmony
          Issue Type: Bug
          Components: DRLVM
            Reporter: Ilya Berezhniuk
            Priority: Minor


When stepping through native code using NCAI, I've got several assertions in encoder.
It's because CMC opcode and D0/D1 shift opcodes are absent (or commented) in decoder tables.

Suggested patch fixes the problem. It adds CMC for decoding only.
D0/D1 opcodes are uncommented and 2nd constant operand was removed because there is no proper
type for it, and only instruction length is needed for JVMTI disassembler.


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