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From "Ilya Berezhniuk (JIRA)" <j...@apache.org>
Subject [jira] Updated: (HARMONY-5321) [drlvm][NCAI][encoder] JVMTI disassembler does not understand CMC opcode and D0/D1 shift opcodes
Date Mon, 17 Dec 2007 14:49:43 GMT

     [ https://issues.apache.org/jira/browse/HARMONY-5321?page=com.atlassian.jira.plugin.system.issuetabpanels:all-tabpanel
]

Ilya Berezhniuk updated HARMONY-5321:
-------------------------------------

    Attachment: H-5321.patch

> [drlvm][NCAI][encoder] JVMTI disassembler does not understand CMC opcode and D0/D1 shift
opcodes
> ------------------------------------------------------------------------------------------------
>
>                 Key: HARMONY-5321
>                 URL: https://issues.apache.org/jira/browse/HARMONY-5321
>             Project: Harmony
>          Issue Type: Bug
>          Components: DRLVM
>            Reporter: Ilya Berezhniuk
>            Priority: Minor
>         Attachments: H-5321.patch
>
>
> When stepping through native code using NCAI, I've got several assertions in encoder.
> It's because CMC opcode and D0/D1 shift opcodes are absent (or commented) in decoder
tables.
> Suggested patch fixes the problem. It adds CMC for decoding only.
> D0/D1 opcodes are uncommented and 2nd constant operand was removed because there is no
proper type for it, and only instruction length is needed for JVMTI disassembler.

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