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From "Evgueni Brevnov (JIRA)" <j...@apache.org>
Subject [jira] Commented: (HARMONY-4621) [drlvm][jit] Stack misalignment when using SSE instructions
Date Thu, 15 Nov 2007 09:19:43 GMT

    [ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel#action_12542717
] 

Evgueni Brevnov commented on HARMONY-4621:
------------------------------------------

I just noticed the following lines in stackalignment_part2.patch

+    // TODO: remove before commit
+    assert((stackSizeAlignment & 15) == 0);

Plz, remove this code before commit.

Thanks
Evgueni

> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
>                 Key: HARMONY-4621
>                 URL: https://issues.apache.org/jira/browse/HARMONY-4621
>             Project: Harmony
>          Issue Type: Improvement
>          Components: DRLVM
>            Reporter: Naumova Natalya 
>            Assignee: Alexey Varlamov
>         Attachments: stackalign_part1.patch, stackalign_part2.patch, stackalign_part2.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading
and storing on 128bit xmm registers,  it increases the performance of SSE usage. Now we have
misalign local variables, and stack register (esp). Then we have a penalty from using xmm
registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp
and all local variables? 

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