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From "Alexey Varlamov (JIRA)" <j...@apache.org>
Subject [jira] Commented: (HARMONY-4621) [drlvm][jit] Stack misalignment when using SSE instructions
Date Thu, 08 Nov 2007 11:17:50 GMT

    [ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel#action_12541026
] 

Alexey Varlamov commented on HARMONY-4621:
------------------------------------------

Oh, another king-size patch. Generally looks good, I only spotted mistyped define in jit_runtime_support_common.h:
#define STACK_ALIGN4         (0x00000008)
BTW, related defines are duplicated thrice, in both JITs and in VM stubs. Moreover, seems
there appears conceptual binding, i.e. alignment should be coherent in VM and JIT. Indeed
this may worth explicit and more articulated interface, need to think about this?


> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
>                 Key: HARMONY-4621
>                 URL: https://issues.apache.org/jira/browse/HARMONY-4621
>             Project: Harmony
>          Issue Type: Improvement
>          Components: DRLVM
>            Reporter: Naumova Natalya 
>            Assignee: Alexey Varlamov
>         Attachments: stackalign_part1.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading
and storing on 128bit xmm registers,  it increases the performance of SSE usage. Now we have
misalign local variables, and stack register (esp). Then we have a penalty from using xmm
registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp
and all local variables? 

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