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From "Mikhail Fursov (JIRA)" <j...@apache.org>
Subject [jira] Created: (HARMONY-4926) [drlvm][jit] Bytecode level edge profile implementation in Jitrino.OPT compiler
Date Thu, 11 Oct 2007 04:21:50 GMT
[drlvm][jit] Bytecode level edge profile implementation in Jitrino.OPT compiler
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                 Key: HARMONY-4926
                 URL: https://issues.apache.org/jira/browse/HARMONY-4926
             Project: Harmony
          Issue Type: New Feature
          Components: DRLVM
            Reporter: Mikhail Fursov
            Assignee: Mikhail Fursov
         Attachments: bclevel_off.patch

The patch contains bc-level edge profile implementation for Jitrino.OPT compiler.
The BC-level edge profile mode is turned off by default in -server mode, because it shows
performance degradation in comparison with IR-based edge profile mapping.
However it can be used to prototype edge profile reusing from any JIT by Jitrino.OPT compiler
(for example passing edge profile from Jitrino.JET to Jitrino.OPT)

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