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From gshiman...@apache.org
Subject svn commit: r583516 - /harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/dec_base.cpp
Date Wed, 10 Oct 2007 15:34:56 GMT
Author: gshimansky
Date: Wed Oct 10 08:34:55 2007
New Revision: 583516

URL: http://svn.apache.org/viewvc?rev=583516&view=rev
Log:
Change disassembler to disassemble 64-bit registers on x86_64 architecture


Modified:
    harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/dec_base.cpp

Modified: harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/dec_base.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/dec_base.cpp?rev=583516&r1=583515&r2=583516&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/dec_base.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/dec_base.cpp Wed Oct 10 08:34:55
2007
@@ -255,6 +255,12 @@
     return false;
 }
 
+#ifdef _IA32_
+#define DISASM_REG_SIZE OpndSize_32
+#else
+#define DISASM_REG_SIZE OpndSize_64
+#endif
+
 bool DecoderBase::decodeModRM(const EncoderBase::OpcodeDesc& odesc,
                               const unsigned char ** pbuf, Inst * pinst)
 {
@@ -273,7 +279,7 @@
     //XXX
     scale=scale; base = base; index = index; disp = disp; reg = reg;
 
-    reg = getRegName(OpndKind_GPReg, OpndSize_32, modrm.reg);
+    reg = getRegName(OpndKind_GPReg, DISASM_REG_SIZE, modrm.reg);
     if (modrm.mod == 3) {
         // we have only modrm. no sib, no disp.
         reg = getRegName(OpndKind_GPReg, opndDesc.size, modrm.rm);
@@ -290,13 +296,13 @@
             // no index
         }
         else {
-            index = getRegName(OpndKind_GPReg, OpndSize_32, sib.index);
+            index = getRegName(OpndKind_GPReg, DISASM_REG_SIZE, sib.index);
         }
-        base = getRegName(OpndKind_GPReg, OpndSize_32, sib.base);
+        base = getRegName(OpndKind_GPReg, DISASM_REG_SIZE, sib.base);
     }
     else {
         if (modrm.mod != 0 || modrm.rm != 5) {
-            base = getRegName(OpndKind_GPReg, OpndSize_32, modrm.rm);
+            base = getRegName(OpndKind_GPReg, DISASM_REG_SIZE, modrm.rm);
         }
         else {
             // mod=0 && rm == 5 => only disp32



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