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From gshiman...@apache.org
Subject svn commit: r583416 - in /harmony/enhanced/drlvm/trunk/vm: port/src/encoder/ia32_em64t/enc_base.cpp port/src/encoder/ia32_em64t/enc_prvt.h port/src/encoder/ia32_em64t/enc_tabl.cpp vmcore/include/jvmti_dasm.h vmcore/src/jvmti/jvmti_dasm.cpp
Date Wed, 10 Oct 2007 10:00:10 GMT
Author: gshimansky
Date: Wed Oct 10 03:00:09 2007
New Revision: 583416

URL: http://svn.apache.org/viewvc?rev=583416&view=rev
Log:
Added x86_64 registers support to the disassembler


Modified:
    harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_base.cpp
    harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h
    harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp
    harmony/enhanced/drlvm/trunk/vm/vmcore/include/jvmti_dasm.h
    harmony/enhanced/drlvm/trunk/vm/vmcore/src/jvmti/jvmti_dasm.cpp

Modified: harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_base.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_base.cpp?rev=583416&r1=583415&r2=583416&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_base.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_base.cpp Wed Oct 10 03:00:09
2007
@@ -21,6 +21,7 @@
 #include "enc_base.h"
 #include <climits>
 #include <string.h>
+#define USE_ENCODER_DEFINES
 #include "enc_prvt.h"
 #include <stdio.h>
 

Modified: harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h?rev=583416&r1=583415&r2=583416&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h (original)
+++ harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h Wed Oct 10 03:00:09
2007
@@ -86,6 +86,7 @@
     OpcodeByteKind_OpcodeMask               = 0x00FF
 };
 
+#ifdef USE_ENCODER_DEFINES
 
 #define N           {0, 0, 0, 0 }
 #define U           {1, 0, 1, OpndRole_Use }
@@ -214,6 +215,8 @@
     #define REX_W   OpcodeByteKind_REX_W
 
 #endif
+
+#endif // USE_ENCODER_DEFINES
 
 /** 
  * @brief Represents the REX part of instruction.

Modified: harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp?rev=583416&r1=583415&r2=583416&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp Wed Oct 10 03:00:09
2007
@@ -34,6 +34,7 @@
     #define _EM64T_
 #endif
 
+#define USE_ENCODER_DEFINES
 #include "enc_prvt.h"
 #include "enc_defs.h"
 

Modified: harmony/enhanced/drlvm/trunk/vm/vmcore/include/jvmti_dasm.h
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/vmcore/include/jvmti_dasm.h?rev=583416&r1=583415&r2=583416&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/vmcore/include/jvmti_dasm.h (original)
+++ harmony/enhanced/drlvm/trunk/vm/vmcore/include/jvmti_dasm.h Wed Oct 10 03:00:09 2007
@@ -46,11 +46,19 @@
         INDIRECT_CALL
     };
     /**
-     * IA-32 general-purpose registers set.
+     * General-purpose registers set.
      */
     enum Register {
-        IA32_REG_NONE, IA32_REG_EAX, IA32_REG_EBX, IA32_REG_ECX,
-        IA32_REG_EDX, IA32_REG_ESI, IA32_REG_EDI, IA32_REG_EBP, IA32_REG_ESP
+        DISASM_REG_NONE,
+#ifdef _IA32_
+        DISASM_REG_EAX, DISASM_REG_EBX, DISASM_REG_ECX, DISASM_REG_EDX,
+        DISASM_REG_ESI, DISASM_REG_EDI, DISASM_REG_EBP, DISASM_REG_ESP
+#elif defined _EM64T_
+        DISASM_REG_RAX, DISASM_REG_RBX, DISASM_REG_RCX, DISASM_REG_RDX,
+        DISASM_REG_RSI, DISASM_REG_RDI, DISASM_REG_RSP, DISASM_REG_RBP,
+        DISASM_REG_R8 , DISASM_REG_R9 , DISASM_REG_R10, DISASM_REG_R11,
+        DISASM_REG_R12, DISASM_REG_R13, DISASM_REG_R14, DISASM_REG_R15
+#endif
     };
     /**
      * Kind of operand 
@@ -71,7 +79,7 @@
         Opnd()
             {
                 kind = Kind_Imm;
-                base = index = reg = IA32_REG_NONE;
+                base = index = reg = DISASM_REG_NONE;
                 scale = 0;
                 disp = 0;
             }

Modified: harmony/enhanced/drlvm/trunk/vm/vmcore/src/jvmti/jvmti_dasm.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/vmcore/src/jvmti/jvmti_dasm.cpp?rev=583416&r1=583415&r2=583416&view=diff
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/vmcore/src/jvmti/jvmti_dasm.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/vmcore/src/jvmti/jvmti_dasm.cpp Wed Oct 10 03:00:09 2007
@@ -33,21 +33,42 @@
 static InstructionDisassembler::Register convertRegName2Register(RegName reg)
 {
     switch(reg) {
-    case RegName_Null:  return InstructionDisassembler::IA32_REG_NONE;
-    case RegName_EAX:   return InstructionDisassembler::IA32_REG_EAX;
-    case RegName_EBX:   return InstructionDisassembler::IA32_REG_EBX;
-    case RegName_ECX:   return InstructionDisassembler::IA32_REG_ECX;
-    case RegName_EDX:   return InstructionDisassembler::IA32_REG_EDX;
-    case RegName_ESI:   return InstructionDisassembler::IA32_REG_ESI;
-    case RegName_EDI:   return InstructionDisassembler::IA32_REG_EDI;
-    case RegName_EBP:   return InstructionDisassembler::IA32_REG_EBP;
-    case RegName_ESP:   return InstructionDisassembler::IA32_REG_ESP;
+#ifdef _IA32_
+    case RegName_Null:  return InstructionDisassembler::DISASM_REG_NONE;
+    case RegName_EAX:   return InstructionDisassembler::DISASM_REG_EAX;
+    case RegName_EBX:   return InstructionDisassembler::DISASM_REG_EBX;
+    case RegName_ECX:   return InstructionDisassembler::DISASM_REG_ECX;
+    case RegName_EDX:   return InstructionDisassembler::DISASM_REG_EDX;
+    case RegName_ESI:   return InstructionDisassembler::DISASM_REG_ESI;
+    case RegName_EDI:   return InstructionDisassembler::DISASM_REG_EDI;
+    case RegName_EBP:   return InstructionDisassembler::DISASM_REG_EBP;
+    case RegName_ESP:   return InstructionDisassembler::DISASM_REG_ESP;
+#elif defined(_EM64T_)
+    case RegName_Null:  return InstructionDisassembler::DISASM_REG_NONE;
+    case RegName_RAX:   return InstructionDisassembler::DISASM_REG_RAX;
+    case RegName_RBX:   return InstructionDisassembler::DISASM_REG_RBX;
+    case RegName_RCX:   return InstructionDisassembler::DISASM_REG_RCX;
+    case RegName_RDX:   return InstructionDisassembler::DISASM_REG_RDX;
+    case RegName_RSI:   return InstructionDisassembler::DISASM_REG_RSI;
+    case RegName_RDI:   return InstructionDisassembler::DISASM_REG_RDI;
+    case RegName_RSP:   return InstructionDisassembler::DISASM_REG_RSP;
+    case RegName_RBP:   return InstructionDisassembler::DISASM_REG_RBP;
+    case RegName_R8 :   return InstructionDisassembler::DISASM_REG_R8;
+    case RegName_R9 :   return InstructionDisassembler::DISASM_REG_R9;
+    case RegName_R10:   return InstructionDisassembler::DISASM_REG_R10;
+    case RegName_R11:   return InstructionDisassembler::DISASM_REG_R11;
+    case RegName_R12:   return InstructionDisassembler::DISASM_REG_R12;
+    case RegName_R13:   return InstructionDisassembler::DISASM_REG_R13;
+    case RegName_R14:   return InstructionDisassembler::DISASM_REG_R14;
+    case RegName_R15:   return InstructionDisassembler::DISASM_REG_R15;
+#endif
     default:
+        assert(0);
         break;
     }
     // Some other registers (e.g. AL or XMM or whatever) - not
     // supported currently
-    return InstructionDisassembler::IA32_REG_NONE;
+    return InstructionDisassembler::DISASM_REG_NONE;
 }
 
 static void convertOperand2Opnd(
@@ -74,7 +95,7 @@
 
 #ifdef _IPF_
 const char* InstructionDisassembler::get_reg_value(
-    InstructionDisassembler::Register reg,
+    Register reg,
     const Registers* pcontext) const
 {
     assert(0);
@@ -84,10 +105,29 @@
 #elif defined _EM64T_
 
 const char* InstructionDisassembler::get_reg_value(
-    InstructionDisassembler::Register reg,
+    Register reg,
     const Registers* pcontext) const
 {
-    assert(0);
+    switch(reg) {
+    case DISASM_REG_NONE: return NULL;
+    case DISASM_REG_RAX:  return (const char*)pcontext->rax;
+    case DISASM_REG_RBX:  return (const char*)pcontext->rbx;
+    case DISASM_REG_RCX:  return (const char*)pcontext->rcx;
+    case DISASM_REG_RDX:  return (const char*)pcontext->rdx;
+    case DISASM_REG_RSI:  return (const char*)pcontext->rsi;
+    case DISASM_REG_RDI:  return (const char*)pcontext->rdi;
+    case DISASM_REG_RBP:  return (const char*)pcontext->rbp;
+    case DISASM_REG_RSP:  return (const char*)pcontext->rsp;
+    case DISASM_REG_R8 :  return (const char*)pcontext->r8 ;
+    case DISASM_REG_R9 :  return (const char*)pcontext->r9 ;
+    case DISASM_REG_R10:  return (const char*)pcontext->r10;
+    case DISASM_REG_R11:  return (const char*)pcontext->r11;
+    case DISASM_REG_R12:  return (const char*)pcontext->r12;
+    case DISASM_REG_R13:  return (const char*)pcontext->r13;
+    case DISASM_REG_R14:  return (const char*)pcontext->r14;
+    case DISASM_REG_R15:  return (const char*)pcontext->r15;
+    default: assert(false);
+    }
     return NULL;
 }
 
@@ -98,15 +138,15 @@
     const Registers* pcontext) const
 {
     switch(reg) {
-    case IA32_REG_NONE: return NULL;
-    case IA32_REG_EAX:  return (const char*)pcontext->eax;
-    case IA32_REG_EBX:  return (const char*)pcontext->ebx;
-    case IA32_REG_ECX:  return (const char*)pcontext->ecx;
-    case IA32_REG_EDX:  return (const char*)pcontext->edx;
-    case IA32_REG_ESI:  return (const char*)pcontext->esi;
-    case IA32_REG_EDI:  return (const char*)pcontext->edi;
-    case IA32_REG_EBP:  return (const char*)pcontext->ebp;
-    case IA32_REG_ESP:  return (const char*)pcontext->esp;
+    case DISASM_REG_NONE: return NULL;
+    case DISASM_REG_EAX:  return (const char*)pcontext->eax;
+    case DISASM_REG_EBX:  return (const char*)pcontext->ebx;
+    case DISASM_REG_ECX:  return (const char*)pcontext->ecx;
+    case DISASM_REG_EDX:  return (const char*)pcontext->edx;
+    case DISASM_REG_ESI:  return (const char*)pcontext->esi;
+    case DISASM_REG_EDI:  return (const char*)pcontext->edi;
+    case DISASM_REG_EBP:  return (const char*)pcontext->ebp;
+    case DISASM_REG_ESP:  return (const char*)pcontext->esp;
     default: assert(false);
     }
     return NULL;
@@ -178,7 +218,7 @@
         {
             const Opnd& op = get_opnd(0);
             if (op.kind == Kind_Reg) {
-                assert(op.reg != IA32_REG_NONE);
+                assert(op.reg != DISASM_REG_NONE);
                 return (NativeCodePtr)get_reg_value(op.reg, pcontext);
             }
             else if (op.kind == Kind_Mem) {



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