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From ndbe...@apache.org
Subject svn commit: r529880 - in /harmony/enhanced/drlvm/trunk/vm/port/src/thread: linux/apr_thread_ext.c win/apr_thread_ext.c
Date Wed, 18 Apr 2007 05:38:47 GMT
Author: ndbeyer
Date: Tue Apr 17 22:38:46 2007
New Revision: 529880

URL: http://svn.apache.org/viewvc?view=rev&rev=529880
Log:
Remove additional 'mfence' instructions to enable execution on P3 (SSE) CPUs.

Modified:
    harmony/enhanced/drlvm/trunk/vm/port/src/thread/linux/apr_thread_ext.c
    harmony/enhanced/drlvm/trunk/vm/port/src/thread/win/apr_thread_ext.c

Modified: harmony/enhanced/drlvm/trunk/vm/port/src/thread/linux/apr_thread_ext.c
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/port/src/thread/linux/apr_thread_ext.c?view=diff&rev=529880&r1=529879&r2=529880
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/port/src/thread/linux/apr_thread_ext.c (original)
+++ harmony/enhanced/drlvm/trunk/vm/port/src/thread/linux/apr_thread_ext.c Tue Apr 17 22:38:46
2007
@@ -105,11 +105,25 @@
 }
 
 APR_DECLARE(void) apr_memory_rw_barrier() {
-    #ifdef _IPF_ 
-        asm volatile ("mf" ::: "memory");
-    #else
-        __asm__("mfence");
-    #endif    
+#if defined(_EM64T_)
+    asm volatile ("mfence" : : : "memory");
+#elif defined(_IPF_)
+    asm volatile ("mf" : : : "memory");
+#else // General x86 case
+    /*
+     * This code must use a lock-prefixed assembly instruction, so that 
+     * we can support P3 processors (SSE2 only). With P4 and SSE3, we 
+     * could use 'mfence'. 
+     * References:
+     * Java Memory Model cookbook 
+     *      - http://gee.cs.oswego.edu/dl/jmm/cookbook.html
+     * Linux Kernel, mb() function 
+     *      - http://lxr.linux.no/source/include/asm-i386/system.h
+     * This is a GCC inline assembly command. The final bit, "memory", will
+     * clobber all of the memory registers.
+     */
+    asm volatile ("lock; addl $0,0(%%esp)" : : : "memory");
+#endif
 }
 
 APR_DECLARE(apr_status_t) apr_thread_times(apr_thread_t *thread, 

Modified: harmony/enhanced/drlvm/trunk/vm/port/src/thread/win/apr_thread_ext.c
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/port/src/thread/win/apr_thread_ext.c?view=diff&rev=529880&r1=529879&r2=529880
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/port/src/thread/win/apr_thread_ext.c (original)
+++ harmony/enhanced/drlvm/trunk/vm/port/src/thread/win/apr_thread_ext.c Tue Apr 17 22:38:46
2007
@@ -24,10 +24,15 @@
 #include "apr_thread_ext.h"
 #include <apr_atomic.h>
 
-#if defined(_EM64T_) && defined(_WIN64)
-#include <intrin.h>
-#pragma intrinsic (_ReadWriteBarrier)
+// MSVC barrier intrinsics setup
+#if _MSC_VER < 1400
+    // VC++ 2003
+    extern void _ReadWriteBarrier();
+#else
+    // VC++ 2005
+    #include <intrin.h>
 #endif
+#pragma intrinsic (_ReadWriteBarrier)
 
 APR_DECLARE(apr_status_t) apr_thread_set_priority(apr_thread_t *thread, 
                 apr_int32_t priority) 
@@ -85,11 +90,7 @@
 }
 
 APR_DECLARE(void) apr_memory_rw_barrier() {
-#if defined(_EM64T_) && defined(_WIN64)
-    _ReadWriteBarrier();
-#else
-    __asm mfence;
-#endif
+	_ReadWriteBarrier();
 }
 
 APR_DECLARE(apr_status_t) apr_thread_times(apr_thread_t *thread, 



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